A display panel includes a substrate, a mark structure, a plurality of active elements, and a plurality of light emitting elements. The mark structure is disposed in a mark region of the display panel. The mark structure includes a drilled layer having a plurality of through holes. The active elements are disposed in an active element region of the display panel. Both the mark region and the active element region are located in a display region of the display panel. The light emitting elements are disposed in the display region of the display panel. A first portion in the light emitting elements is overlapped with the mark structure in a normal direction of a surface of the substrate.

A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.