A semiconductor device is provided with: a semiconductor chip die-bonding mounted face up on a support; an intermediate substrate connecting the semiconductor chip to a plurality of external connection portions; and a plurality of connection bumps connecting the semiconductor chip and the intermediate substrate. The plurality of connection bumps includes a plurality of power supply bumps connected to a plurality of electrode pads on the semiconductor chip for supplying power to the semiconductor chip. The intermediate substrate includes: a plurality of power supply pads connected to the plurality of electrode pads through the plurality of power supply bumps; a bump surface facing the semiconductor chip and having a plurality of power supply pads formed thereon; an external connection surface having a plurality of external connection pads formed thereon connected to the external connection portions; and a capacitor connected to the plurality of power supply bumps.

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

A semiconductor package includes: a package substrate including first and second sides that are opposite to each other, and including an insulating member and a plurality of redistribution layers; a semiconductor chip disposed on the first side and including a plurality of contact pads that are connected to a first redistribution layer of the plurality of redistribution layers; a protective layer disposed on the second side and exposing a portion of a second redistribution layer of the plurality of redistribution layers; a plurality of under bump metallurgy (UBM) pads disposed on the second side and connected to the exposed portion of the second redistribution layer; a dummy pattern formed on the protective layer; an insulating pattern covering the dummy pattern; and a passive element disposed on the insulating pattern and a first set of UBM pads of the plurality of UBM pads.

A semiconductor package includes a lower semiconductor chip and semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip. Connection bumps are between the lower semiconductor chip and a bottommost one of the semiconductor chips and between the semiconductor chips, A protection layer covers a lateral surface of each of the connection bumps. A mold layer is on the lower semiconductor chip and covering lateral surfaces of the semiconductor chips. The mold layer extends between the bottommost one of the semiconductor chips and the lower semiconductor chip and between the semiconductor chips. The protection layer is between the mold layer and the lateral surface of each of the connection bumps.

A package comprising a first substrate; a first integrated device coupled to the first substrate; an interconnection die coupled to the first substrate; a second substrate coupled to the first substrate through the interconnection die such that the first integrated device and the interconnection die are located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate.