In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower surface; a conductive pillar formed on the upper surface of the conductor layer and having an upper surface, a lower surface, and a sidewall; a protection film covering the upper surface of the conductor layer and having an opening which exposes the upper surface and the sidewall of the conductive pillar; and a protection film covering the sidewall of the conductive pillar. Then, in plan view, the opening of the protection film is wider than the upper surface of the conductive pillar and exposes an entire region of an upper surface of the conductive pillar.

The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower surface; a conductive pillar formed on the upper surface of the conductor layer and having an upper surface, a lower surface, and a sidewall; a protection film covering the upper surface of the conductor layer and having an opening which exposes the upper surface and the sidewall of the conductive pillar; and a protection film covering the sidewall of the conductive pillar. Then, in plan view, the opening of the protection film is wider than the upper surface of the conductive pillar and exposes an entire region of an upper surface of the conductive pillar.