A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Package deflection and mechanical stress of microelectronic packaging is minimized in a two step manufacturing process. In a first step, a ceramic insulator is high-temperature bonded between a wraparound lead layer and a buffer layer of a same material as the lead layer to provide a symmetrically balanced three-layer structure. In a second step, the three-layer structure is high temperature bonded, using a lower melt point braze, to a heat spreader. This package configuration minimizes package deflection, and thereby improves thermal dissipation and reliability of the package.

A computing device is provided with a slot that includes a first locking element and a second locking element configured to receive a removable computing device carrier. The computing device carrier includes a bracket for securing a first computing device in a first receiving space, and second computing device in a second receiving space. The bracket also includes a first latching mechanism configured to secure the first locking element of the slot, and a second latching mechanism configured to secure the second locking element of the slot. The computing device carrier also includes a frame secured to the bracket. The frame includes a first end with a first guide slot, and a second end with a second guide slot. The first and second guide slots are configured to enable the computing device carrier to adjust from a first position to a second position while secured within the slot.

A computing device is provided with a slot that includes a first locking element and a second locking element configured to receive a removable general purpose graphic processing unit (GPGPU) carrier. The GPGPU carrier includes a bracket for securing a first GPGPU in a first receiving space, and second GPGPU in a second receiving space. The bracket also includes a first latching mechanism configured to secure the first locking element of the slot, and a second latching mechanism configured to secure the second locking element of the slot. The GPGPU carrier also includes a frame secured to the bracket. The frame includes a first end with a first guide slot, and a second end with a second guide slot, configured to secure the GPGPU carrier within the slot. The first and second guide slots are configured to enable the GPGPU carrier to adjust from a first position to a second position while secured within the slot.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

A computing device is provided with a slot that includes a first locking element and a second locking element configured to receive a removable general purpose graphic processing unit (GPGPU) carrier. The GPGPU carrier includes a bracket for securing a first GPGPU in a first receiving space, and second GPGPU in a second receiving space. The bracket also includes a first latching mechanism configured to secure the first locking element of the slot, and a second latching mechanism configured to secure the second locking element of the slot. The GPGPU carrier also includes a frame secured to the bracket. The frame includes a first end with a first guide slot, and a second end with a second guide slot. The first and second guide slots are configured to enable the GPGPU carrier to adjust from a first position to a second position while secured within the slot.

Package deflection and mechanical stress of microelectronic packaging is minimized in a two step manufacturing process. In a first step, a ceramic insulator is high-temperature bonded between a wraparound lead layer and a buffer layer of a same material as the lead layer to provide a symmetrically balanced three-layer structure. In a second step, the three-layer structure is high temperature bonded, using a lower melt point braze, to a heat spreader. This package configuration minimizes package deflection, and thereby improves thermal dissipation and reliability of the package.

An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.

A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.