An electronic protection switch includes first and second network terminals and two semiconductor switches of same kind. Each semiconductor switch is formed by an IGBT semiconductor switch and includes a switching element and a diode which is arranged antiparallel to the switching element. A first of the two semiconductor switches is arranged without a semiconductor series connection between a positive potential terminal of the first network terminal and a positive potential terminal of the second network terminal. A second of the two semiconductor switches is arranged without a semiconductor series connection between a negative potential terminal of the first network terminal and a negative potential terminal of the second network terminal. The switching element of each semiconductor switch is arranged so as to be able to conduct and switch off a current from the first network terminal to the second network terminal.

A switch control circuit includes a power switch, a first protection unit, and a second protection unit. The power switch has a first terminal coupled to a first voltage terminal for receiving a first voltage, a second terminal coupled to a second voltage terminal for receiving a second voltage, and a control terminal receives a control voltage. In a first mode, the control voltage is greater than the first voltage. In a second mode, when a voltage of the second voltage terminal is smaller than a first reference voltage, the first protection unit pulls down the control voltage to reduce a current flowing through the power switch. When the voltage of the second voltage terminal is smaller than the second reference voltage, the second protection unit pulls down the control voltage to a ground voltage.

An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

The problem to be solved is to provide a system and a method to protect the regulator rectifiers from the reverse voltage condition and the short circuit condition, and the problem is solved in the present invention by a system and a method that use a protection device including a control unit that receives an input from the circuit based on the reverse voltage condition and the short circuit condition, and based on the existence of at least one of the condition or a combination thereof, the control unit switches a switching unit from an ON state to an OFF state, thereby breaking the circuit between the regulator rectifier device and the load section, thus protecting the regulator rectifier device.

A triggering circuit and an electronic fuse device incorporating the same. The triggering circuit works with a microcontroller to control a load. The microcontroller has a low-power mode and an external interrupt input for triggering wakeup from the low-power mode and initiating an interrupt action related to the load. The triggering circuit comprises a sensor input for receiving a sensor signal related to the load, a threshold input for receiving a threshold reference signal, and a comparator for comparing the sensor signal to the threshold reference signal and for outputting an interrupt signal to the external interrupt input in response to the comparison.

A secondary battery protection circuit for a secondary battery includes: a reference voltage circuit configured to generate a reference voltage by using a depletion-type transistor and a transistor unit of enhancement type connected in series with the depletion-type transistor; a voltage divider configured to output a detection voltage obtained by dividing a power source voltage of the secondary battery; a detection circuit configured to detect an abnormal state of the secondary battery based on the reference voltage and the detection voltage; a first adjustment circuit configured to adjust a size ratio of the depletion-type transistor to the transistor unit based on threshold voltages of the depletion-type transistor and the transistor unit; and a second adjustment circuit configured to adjust the detection voltage based on the reference voltage after adjusting the size ratio.

An electrical protection system arranged to detect and isolate faults either in a electrical power distribution. The system comprises at least a first busbar and a second busbar in electrical communication with each other through s powerline having a first end electrically coupled to the first busbar by a first circuit breaker and a second end connected to the second busbar by a second circuit breaker. It is connected to the at least two busbars, and configured to simultaneously collect/determine a first electrical quantity at each of the at least two busbars and compare the collected/determined electrical quantity to a second. When the first electrical quantity value less than the second quantity value, the system causes the first and second circuit breakers to open so as to decouple the electrical connection between first and second busbars. The system 100 detects and isolates fault efficiently while using voltage measurements.

A semiconductor device includes first and second protection circuits. The first protection circuit includes a timer circuit, a voltage detection circuit, and a discharge element. The second protection circuit includes a discharge circuit. The timer circuit is connected between a first pad on a power supply potential side and a second pad on a reference potential side. The voltage detection circuit is connected between the first and second pads on an output side of the timer circuit. The discharge element is connected between the first and second pads on an output side of the voltage detection circuit. The discharge circuit is connected between a third pad on the power supply potential side and a fourth pad on the reference potential side on the output side of the timer circuit.

In accordance with an embodiment, a circuit includes: a supply pin and an output pin for connecting a load, and a configuration pin; a semiconductor switch connected between the supply pin and the output pin and configured to establish or to block a current path between the supply pin and the output pin depending on a control signal; and a control circuit configured to generate the control signal for the semiconductor switch taking account of a first parameter, and set the first parameter depending on a component parameter of an external component connected to the configuration pin. The first parameter is set to a first standard value when the component parameter is less than a first threshold value, and the first parameter is set to a second standard value when the component parameter is greater than a second threshold value.

An auto recovery circuit breaker (ARCB) device is disclosed that may include a step-down transformer which may provide a low voltage AC test signal to detect a fault in a phase line or neutral of an electric circuit. A first current transformer (CT) is positioned on the first line, and a second CT is positioned on the second line. Each of the first CT and the second CT may sense a current flowing through the electric circuit, and detect an earth leakage through the electric circuit. A microcontroller is configured to: monitor the analog signal in the circuit, detect earth leakage before powering ON the circuit, detect output short before power ON, and upon detection of a fault removal in the electrical circuit, turn ON a relay. Once turned ON, the ARCB device may continue test by sensing the CT’s provided in the phase and neutral lines.