A terminal protection voltage detector circuit is provided for protecting a terminal block having output terminals in a power supply apparatus. A current detector detects output currents flowing from the power supply apparatus to loads via output terminals, and a first comparator configured to compare a sum of the detected output currents with a predetermined first threshold and output a first comparison result signal when the sum of output currents is larger than or equal to the first threshold. A second comparator configured to compare a maximum value of detected output currents with a predetermined second threshold and output a second comparison result signal when the maximum value is equal to or larger than the second threshold. A current stop circuit stops a current from flowing from the power supply apparatus to the output terminals based on the first or second comparison result signal.

An electrical circuit protection device a processor-based controller configured to operate at least one solid state switching element in a manner responsive to a variety of different time-current conditions to protect a plurality of different electrical loads. A field deployable adaptor device is configured to communicate with the controller. The controller is configured with at least one pre-preprogrammed control algorithm or at least one selected setting for a control algorithm executable by the controller. At least one pre-preprogrammed control algorithm or at least one selected setting are predetermined by a manufacturer of the circuit protector device.

A microgrid overcurrent protection device and a method for overcurrent protection of a microgrid. The protection device including a voltage controlled overcurrent detector for detecting an overcurrent above an overcurrent threshold and a phase directional detector arranged for current direction in a downstream or an upstream direction. The overcurrent threshold of the voltage controlled overcurrent detector is set at an upper overcurrent threshold when a measured voltage Vm is above a threshold voltage Vs and set at a lower overcurrent threshold when the measured voltage Vm is below the threshold voltage Vs. The device further includes a timer arranged for generating a trigger signal with a first delay time period when a downstream current direction and an overcurrent are detected and with a second delay time period when an upstream current direction and an overcurrent are detected.

A microgrid overcurrent protection device and a method for overcurrent protection of a microgrid. The protection device including a voltage controlled overcurrent detector for detecting an overcurrent above an overcurrent threshold and a phase directional detector arranged for current direction in a downstream or an upstream direction. The overcurrent threshold of the voltage controlled overcurrent detector is set at an upper overcurrent threshold when a measured voltage Vm is above a threshold voltage Vs and set at a lower overcurrent threshold when the measured voltage Vm is below the threshold voltage Vs. The device further includes a timer arranged for generating a trigger signal with a first delay time period when a downstream current direction and an overcurrent are detected and with a second delay time period when an upstream current direction and an overcurrent are detected.

Digital isolator devices, and many other devices, have a maximum device junction temperature, which, if exceeded, may cause device failure and the integrity of the isolation is no longer guaranteed. The use of an electronic fuse, eFuse, arranged in series with the digital isolator, provides a protection scheme for the digital isolator in which current is limited by the eFuse when it is determined that the supply current of the digital isolator exceeds a predetermined threshold that would the cause junction temperature to increase above an absolute maximum rating. As such, the integrity of the digital isolator is preserved in the event of a system fault.

Digital isolator devices, and many other devices, have a maximum device junction temperature, which, if exceeded, may cause device failure and the integrity of the isolation is no longer guaranteed. The use of an electronic fuse, eFuse, arranged in series with the digital isolator, provides a protection scheme for the digital isolator in which current is limited by the eFuse when it is determined that the supply current of the digital isolator exceeds a predetermined threshold that would the cause junction temperature to increase above an absolute maximum rating. As such, the integrity of the digital isolator is preserved in the event of a system fault.

According to one aspect of the present disclosure, an energy storage system includes one or more power sources, one or more energy storage components, and one or more solid state circuit breakers disposed between the one or more power sources and the one or more energy storage components such that electrical power is exchanged between the one or more power sources to the one or more energy storage components through the one or more solid state circuit breakers. The energy storage system also includes a controller configured to operate the one or more solid state circuit breakers to control current exchanged with the one or more energy storage components and protect the one or more energy storage components from the one or more power sources during a fault condition.

A circuit for detecting faults affecting a power transistor comprises a conditioning circuit, a first fault status circuit, and a fault signaling circuit. The power transistor is turned on and off by assertion and de-assertion, respectively, of an input signal. The conditioning circuit produces a conditioned gate voltage signal from a gate voltage of the power transistor. The first fault status circuit asserts a first fault indication when the conditioned gate voltage signal is greater than a first fault reference voltage during a first interval after the assertion of the input signal. The fault signaling circuit asserts a fault signal in response to the first fault indication being asserted, and de-asserting the fault signal in response to the input signal being de-asserted.

A circuit for detecting faults affecting a power transistor comprises a conditioning circuit, a first fault status circuit, and a fault signaling circuit. The power transistor is turned on and off by assertion and de-assertion, respectively, of an input signal. The conditioning circuit produces a conditioned gate voltage signal from a gate voltage of the power transistor. The first fault status circuit asserts a first fault indication when the conditioned gate voltage signal is greater than a first fault reference voltage during a first interval after the assertion of the input signal. The fault signaling circuit asserts a fault signal in response to the first fault indication being asserted, and de-asserting the fault signal in response to the input signal being de-asserted.

A circuit breaker distribution system is configured to provide selective coordination. The system comprises a solid-state switch disposed as a main or upstream breaker and a switch with an over current protection disposed as a branch or downstream breaker. The solid-state switch comprises a microcontroller to: allow repeated pulses of current through to the branch or downstream breaker in an event of an overload or short circuit, choose a maximum current limit for the solid-state switch as a “chop level” such that the chop level is chosen higher than a rated current of the solid-state circuit breaker but low enough that the solid-state switch is not damaged from repeated pulses over a period of time needed to switch OFF the branch or downstream breaker, and add a pulse interval which is optimized to a system voltage waveform in that chopped pulses tend to be longer and more effective for de-latching the branch or downstream breaker when they occur in vicinity of a zero crossing of the system voltage waveform and chopped pulses are shorter and less effective near peaks of the system voltage waveform.