An AC arc fault detection module includes an LF current section, an LF voltage section, and an HF current section having a plurality of outputs, each output being associated with a respective one of a plurality of frequency sub-bands. The HF current section is structured to, for each of the frequency sub-bands, (i) detect a rise in energy of the frequency sub-band above a first predetermined threshold level for at least a certain amount of time and (ii) cause the associated output to indicate a rise in energy detection in response to detecting the rise in energy above the associated threshold level for at least the associated certain amount of time. The module includes a processing device structured to determine whether an AC arc fault has occurred based on the outputs from the LF and HF current and LF voltage sections.

An AC arc fault detection module includes an LF current section, an LF voltage section, and an HF current section having a plurality of outputs, each output being associated with a respective one of a plurality of frequency sub-bands. The HF current section is structured to, for each of the frequency sub-bands, (i) detect a rise in energy of the frequency sub-band above a first predetermined threshold level for at least a certain amount of time and (ii) cause the associated output to indicate a rise in energy detection in response to detecting the rise in energy above the associated threshold level for at least the associated certain amount of time. The module includes a processing device structured to determine whether an AC arc fault has occurred based on the outputs from the LF and HF current and LF voltage sections.

A DC arc fault detection module includes an LF current section, an LF voltage section, and an HF current section having a plurality of outputs, each output being associated with a respective one of a plurality of frequency sub-bands. The HF current section is structured to, for each of the frequency sub-bands, (i) detect a rise in energy of the frequency sub-band above a first predetermined threshold level for at least a certain amount of time and (ii) cause the associated output to indicate a rise in energy detection in response to detecting the rise in energy above the associated threshold level for at least the associated certain amount of time. The module includes a processing device structured to determine whether a DC arc fault has occurred based on the outputs from the LF and HF current and LF voltage sections.

A DC arc fault detection module includes an LF current section, an LF voltage section, and an HF current section having a plurality of outputs, each output being associated with a respective one of a plurality of frequency sub-bands. The HF current section is structured to, for each of the frequency sub-bands, (i) detect a rise in energy of the frequency sub-band above a first predetermined threshold level for at least a certain amount of time and (ii) cause the associated output to indicate a rise in energy detection in response to detecting the rise in energy above the associated threshold level for at least the associated certain amount of time. The module includes a processing device structured to determine whether a DC arc fault has occurred based on the outputs from the LF and HF current and LF voltage sections.

A semiconductor device, overvoltage detection structure is described that includes a current path including a Zener diode connected in series with a fuse. The Zener diode is configured to conduct a current in response to an overvoltage condition at a semiconductor device and the fuse is configured to permanently break the current path of the overvoltage detection structure in response to the Zener diode conducting the current.

A semiconductor device, overvoltage detection structure is described that includes a current path including a Zener diode connected in series with a fuse. The Zener diode is configured to conduct a current in response to an overvoltage condition at a semiconductor device and the fuse is configured to permanently break the current path of the overvoltage detection structure in response to the Zener diode conducting the current.

Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.

A multi-channel transient voltage suppressor includes a plurality of diode strings, a Zener diode and a diode array. The diode strings respectively have a plurality of input output terminals. The diode array includes a first bypass diode and a second bypass diode. The first bypass diode is coupled between a common bus and a ground terminal, and provides a forward turned-on path from the ground terminal to the common bus. The second bypass diode is coupled to the first bypass diode in parallel, and provides a reverse turned-on path from the common bus to the ground terminal. A current dissipation path is formed between each of the input output terminals and the ground terminal by the diode array.

A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.

A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.