An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.

An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.

A driver circuit is configured to control a power transistor. The driver circuit comprises a signal generator configured to generate a control signal for the power transistor based on a supply signal and an input signal from a control unit. In addition, the driver circuit includes a ripple detector configured to receive the supply signal and determine whether the supply signal includes a ripple error. In some examples, the ripple detector may be configured to send a warning signal to the control unit in response to detecting the ripple error.

A driver circuit is configured to control a power transistor. The driver circuit comprises a signal generator configured to generate a control signal for the power transistor based on a supply signal and an input signal from a control unit. In addition, the driver circuit includes a ripple detector configured to receive the supply signal and determine whether the supply signal includes a ripple error. In some examples, the ripple detector may be configured to send a warning signal to the control unit in response to detecting the ripple error.

A driving circuit providing a driving signal at a driving terminal to drive a power switch. The driving signal has a first driving period and a second driving period. Both the first driving period and the second driving period have a first driving time interval. The driving circuit has a first equivalent on resistor established during the first driving time interval and located between a first voltage node and the driving terminal. The first equivalent on resistor has a first equivalent on resistance during the first driving time interval of the first driving period and has a second equivalent on resistance during the first driving time interval of the second driving period. The first equivalent on resistance and the second equivalent on resistance are not equal.

A driving circuit providing a driving signal at a driving terminal to drive a power switch. The driving signal has a first driving period and a second driving period. Both the first driving period and the second driving period have a first driving time interval. The driving circuit has a first equivalent on resistor established during the first driving time interval and located between a first voltage node and the driving terminal. The first equivalent on resistor has a first equivalent on resistance during the first driving time interval of the first driving period and has a second equivalent on resistance during the first driving time interval of the second driving period. The first equivalent on resistance and the second equivalent on resistance are not equal.

A shoot-through protection circuit includes a current sensor providing a sensor signal connected to a comparator input via at least a burden resistor. A switch protection circuit including a protection input connected to an output of the comparator and a plurality of outputs. Each of the outputs is connected to a corresponding switch in a plurality of stacked switches. Wherein the switch protection circuit is configured to drive each switch of the plurality of stacked switches open in response to a positive output signal from the comparator.

A shoot-through protection circuit includes a current sensor providing a sensor signal connected to a comparator input via at least a burden resistor. A switch protection circuit including a protection input connected to an output of the comparator and a plurality of outputs. Each of the outputs is connected to a corresponding switch in a plurality of stacked switches. Wherein the switch protection circuit is configured to drive each switch of the plurality of stacked switches open in response to a positive output signal from the comparator.

A semiconductor device including: NMOS transistors respectively having the drains, which are connectable to respective second terminals of boot capacitors of which respective first terminals are connectable to respective nodes at which high-side transistors and the low-side transistors are connected together, and the sources, which are electrically connectable to an application terminal for a supply voltage; and controllers driving respective gates of the plurality of NMOS transistors. When the high-side transistor for a first channel is kept off by the driver for the first channel, the high-side transistor for a second channel, which is different from the first channel, is kept on by the driver for the second channel. The controller for the first channel feeds a drive voltage based on the boot voltage for the second channel to the gate of the NMOS transistor for the first channel to keep on the NMOS transistor.

Provided is a control unit of a power conversion device configured to select, in each first set cycle, a first target switching element and a second target switching element from a plurality of switching elements connected in parallel to each other. The control unit performs control so that, at a time of a turn-on operation of a switching circuit, a turn-on start time of the first target switching element is earlier by a first set time period than a turn-on start time of another switching element that is not the first target switching element. The control unit performs control so that, at a time of a turn-off operation of the switching circuit, a turn-off start time of the second target switching element is later by a second set time period than a turn-off start time of another switching element that is not the second target switching element.