The present disclosure relates to a reconfigurable multicore inductor capacitor (LC) oscillator comprising a plurality of oscillator cores. The oscillator may be configured at run-time, at manufacturing, or at production, which may allow for the tailoring of operating characteristics of the oscillator, such as phase noise, electromagnetic interference, or power consumption, for a specific application after production. The cores are coupled through an interconnect network to a common electrical signal output. A subset of the cores may be selectively enabled while the remainder of the cores is disabled. The ability to enable only a subset of the cores allows the total number of enabled cores to be reconfigurable. Furthermore, the direction in which oscillation current flows through the inductor of the cores may be configured. Reconfiguring the number of enabled cores and/or the oscillation current direction in the cores allow operating characteristics of the oscillator to be tailored after production.

An oscillator apparatus includes an oscillator core circuit. The oscillator core circuit includes an inverting transconductance amplifier, at least one first capacitor, at least one second capacitor, and a resonator. The at least one first capacitor is connected between an input of the inverting transconductance amplifier and a ground level. The at least one second capacitor is connected between an output of the inverting transconductance amplifier and the ground level. The resonator has a first port connected to the input of the inverting transconductance amplifier and a second port connected to the output of the inverting transconductance amplifier. The first port is decoupled from the second port.

An oscillator apparatus includes an oscillator core circuit. The oscillator core circuit includes an inverting transconductance amplifier, at least one first capacitor, at least one second capacitor, and a resonator. The at least one first capacitor is connected between an input of the inverting transconductance amplifier and a ground level. The at least one second capacitor is connected between an output of the inverting transconductance amplifier and the ground level. The resonator has a first port connected to the input of the inverting transconductance amplifier and a second port connected to the output of the inverting transconductance amplifier. The first port is decoupled from the second port.

A crystal oscillator circuit comprises a crystal; oscillator circuitry for generating a crystal oscillation signal at an oscillation frequency; and a kick-start circuit for injecting pulses into the crystal during a start-up period. The oscillator circuitry comprises a differential pair of transistors and can operate in an oscillating mode or a start-up mode. In the oscillating mode, the differential pair of transistors is cross-coupled so that a gate terminal of one transistor is coupled to a drain terminal of the other transistor, and vice versa, and the drain terminals are coupled to the crystal to generate the crystal oscillation signal. In the start-up mode, the kick-start circuit drives the gate terminals of the transistors with said pulses. This crystal oscillator circuit has a decreased start-up time compared to prior art solutions and a reduced influence of parasitic oscillations.

A crystal oscillator circuit comprises a crystal; oscillator circuitry for generating a crystal oscillation signal at an oscillation frequency; and a kick-start circuit for injecting pulses into the crystal during a start-up period. The oscillator circuitry comprises a differential pair of transistors and can operate in an oscillating mode or a start-up mode. In the oscillating mode, the differential pair of transistors is cross-coupled so that a gate terminal of one transistor is coupled to a drain terminal of the other transistor, and vice versa, and the drain terminals are coupled to the crystal to generate the crystal oscillation signal. In the start-up mode, the kick-start circuit drives the gate terminals of the transistors with said pulses. This crystal oscillator circuit has a decreased start-up time compared to prior art solutions and a reduced influence of parasitic oscillations.

In a quartz crystal unit, the unit comprising a quartz crystal resonator having a base portion, and first and second tuning fork arms connected to the base portion, the base portion having a length less than 0.5 mm and greater than a spaced-apart distance between the first and second tuning fork arms, each of the first and second tuning fork arms having a width less than 0.1 mm and a length less than 1.56 mm, and a plurality of different widths including a first width and a second width greater than the first width, at least one groove being formed in at least one of opposite main surfaces of each of the first and second tuning fork arms so that a length of the at least one groove is within a range of 0.3 mm to 0.79 mm, the quartz crystal resonator being housed in a case, and a lid being connected to the case.

In a quartz crystal unit, the unit comprising a quartz crystal resonator having a base portion, and first and second tuning fork arms connected to the base portion, the base portion having a length less than 0.5 mm and greater than a spaced-apart distance between the first and second tuning fork arms, each of the first and second tuning fork arms having a width less than 0.1 mm and a length less than 1.56 mm, and a plurality of different widths including a first width and a second width greater than the first width, at least one groove being formed in at least one of opposite main surfaces of each of the first and second tuning fork arms so that a length of the at least one groove is within a range of 0.3 mm to 0.79 mm, the quartz crystal resonator being housed in a case, and a lid being connected to the case.

A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.

A circuit includes: an oscillator configured to generate an oscillation clock signal; an NMOS transistor having a source connected with a power terminal of the oscillator, and a drain connected with a first power supply line to which a first power supply voltage is supplied; an operational amplifier configured to control a gate voltage of the NMOS transistor based on a voltage of the power terminal of the oscillator; and a charge pump. The charge pump is configured to use the oscillation clock signal or a clock signal generated from the oscillation clock signal to boost the first power supply voltage and generate a boosted power supply voltage, and to supply the boosted power supply voltage to the power terminal of the operational amplifier.

A circuit includes: an oscillator configured to generate an oscillation clock signal; an NMOS transistor having a source connected with a power terminal of the oscillator, and a drain connected with a first power supply line to which a first power supply voltage is supplied; an operational amplifier configured to control a gate voltage of the NMOS transistor based on a voltage of the power terminal of the oscillator; and a charge pump. The charge pump is configured to use the oscillation clock signal or a clock signal generated from the oscillation clock signal to boost the first power supply voltage and generate a boosted power supply voltage, and to supply the boosted power supply voltage to the power terminal of the operational amplifier.