A resistor-capacitor oscillation circuit includes a first group of inverters, a second group of inverters, a latch, a delay circuit, and a third group of inverters. The first group of the inverters is connected to the delay circuit and is configured to generate a first signal A and a second signal B. An input end of the second group of the inverters is connected to an enable signal EN. An output end of the second group of the inverters is connected to the latch. An output end of the delay circuit is connected to the latch. The latch is connected to the third group of the inverters and includes a first output end and a second output end. After a first clock signal FB is driven by the third group of the inverters, an output signal CLK is output by an output end of the third group.

A resistor-capacitor oscillation circuit includes a first group of inverters, a second group of inverters, a latch, a delay circuit, and a third group of inverters. The first group of the inverters is connected to the delay circuit and is configured to generate a first signal A and a second signal B. An input end of the second group of the inverters is connected to an enable signal EN. An output end of the second group of the inverters is connected to the latch. An output end of the delay circuit is connected to the latch. The latch is connected to the third group of the inverters and includes a first output end and a second output end. After a first clock signal FB is driven by the third group of the inverters, an output signal CLK is output by an output end of the third group.

Some aspects of the present disclosure relate to detection of a Phase Hit and, upon detecting the Phase Hit, determining the magnitude and location of the Phase Hit. Detecting the Phase Hit may involve comparing a phase offset difference for successive pilot symbol to a detection threshold. Determination of the detection threshold may involve a Neyman-Pearson binary hypothesis testing (NP-BHT) approach. Once the magnitude and location of the Phase Hit are known, data symbols received after the location may be processed to remove the magnitude of the Phase Hit.

Some aspects of the present disclosure relate to detection of a Phase Hit and, upon detecting the Phase Hit, determining the magnitude and location of the Phase Hit. Detecting the Phase Hit may involve comparing a phase offset difference for successive pilot symbol to a detection threshold. Determination of the detection threshold may involve a Neyman-Pearson binary hypothesis testing (NP-BHT) approach. Once the magnitude and location of the Phase Hit are known, data symbols received after the location may be processed to remove the magnitude of the Phase Hit.

A system for transmitting power and data through a two pin connection interface may have a first device having a power source, a first microcontroller with a first communication peripheral coupled with a first pin and a first control port coupled with a gate of a first MOSFET whose switch path couples the power source with the first pin; and a second device having a battery, a second microcontroller with a second communication peripheral coupled with a first pin and a second control port coupled with a gate of a second MOSFET whose switch path couples the battery with the first pin of the second device. When the devices are coupled, the MOSFETs are synchronously turned on and off, wherein during an off-cycle a data transfer between the first and second device takes place through the first and second communication peripherals of the first and second device, respectively.

Embodiments may relate to a structure to be used in a neural network. A first column and a second column, both of which are to couple with a substrate. A capacitor structure may be electrically coupled with the first column. An insulator-metal transition (IMT) structure may be coupled with the first column such that the capacitor structure is electrically positioned between the IMT structure and the first column. A resistor structure may further be electrically coupled with the IMT structure and the second column such that the resistor structure is electrically positioned between the second column and the IMT structure. Other embodiments may be described or claimed.

Embodiments may relate to a structure to be used in a neural network. A first column and a second column, both of which are to couple with a substrate. A capacitor structure may be electrically coupled with the first column. An insulator-metal transition (IMT) structure may be coupled with the first column such that the capacitor structure is electrically positioned between the IMT structure and the first column. A resistor structure may further be electrically coupled with the IMT structure and the second column such that the resistor structure is electrically positioned between the second column and the IMT structure. Other embodiments may be described or claimed.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

An oscillator circuit includes an amplifying unit and a first feedback resistor. The amplifying unit includes an inverter at an input stage being connected to the one end of a crystal resonator, an inverter at an output stage being connected to the other end of the crystal resonator, and a linear amplifier. The linear amplifier is connected between an output terminal of the inverter at the input stage and an input terminal of the inverter at the output stage. The linear amplifier includes at least one inverter and a second feedback resistor. The second feedback resistor is connected in parallel to the at least one inverter. The linear amplifier has a conductance with a magnitude larger than a conductance of the inverter at the input stage and equal to or less than a conductance of the inverter at the output stage.