A transmission system comprising: an output-terminal configured to provide an output-signal; a phase-shift oscillator comprising a plurality of phase-shifters, each configured to provide one of a plurality of phase-shifted-signals; and a controller configured to provide a selected one of the phase-shifted-signals to the output-signal as a transition in the output-signal, at an instant in time that is based on one or more of the plurality of phase-shifted-signals.

A technique for tuning a ladder-shaped inductor that achieves a finer tuning resolution by severing one or more shorts, skipping the severing of one or more shorts, and severing one or more subsequent shorts within the ladder-shaped inductor. This technique can be applied to a voltage-controlled oscillator using a differential or single-ended ladder-shaped inductor as part of the resonant circuit. Within an oscillator, such a technique provides for a more precise modulation of the effective inductance of the ladder-shaped inductor, which enables an improved tuning resolution of the operating frequency of the oscillator.

A technique for tuning a ladder-shaped inductor that achieves a finer tuning resolution by severing one or more shorts, skipping the severing of one or more shorts, and severing one or more subsequent shorts within the ladder-shaped inductor. This technique can be applied to a voltage-controlled oscillator using a differential or single-ended ladder-shaped inductor as part of the resonant circuit. Within an oscillator, such a technique provides for a more precise modulation of the effective inductance of the ladder-shaped inductor, which enables an improved tuning resolution of the operating frequency of the oscillator.

A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.

A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.

A method and device for calibrating an RC oscillator, a storage medium and a processor are provided. The method may include: in a first communication time period, a frequency of a first RC oscillator is adjusted at a first communication frequency point; at the first communication frequency point, the frequency of the first RC oscillator is adjusted according to a default gear of the first RC oscillator sequentially, and at least one of a corresponding gear value and a corresponding frequency when the first device end may receive or may not receive data sent by a second device end is recorded; a first target frequency and a first target gear value of the first RC oscillator are determined according to the at least one of a corresponding gear value and a corresponding frequency; and the first device end is controlled to communicate with the second device end at a second communication frequency point which is determined by the first target gear value in a second communication time period.

A method and device for calibrating an RC oscillator, a storage medium and a processor are provided. The method may include: in a first communication time period, a frequency of a first RC oscillator is adjusted at a first communication frequency point; at the first communication frequency point, the frequency of the first RC oscillator is adjusted according to a default gear of the first RC oscillator sequentially, and at least one of a corresponding gear value and a corresponding frequency when the first device end may receive or may not receive data sent by a second device end is recorded; a first target frequency and a first target gear value of the first RC oscillator are determined according to the at least one of a corresponding gear value and a corresponding frequency; and the first device end is controlled to communicate with the second device end at a second communication frequency point which is determined by the first target gear value in a second communication time period.

A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.

A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.

A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.