A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Embodiments of the present disclosure disclose a clock frequency detection method and apparatus. The method includes: dividing a known internal clock frequency range of the system into n frequency intervals, where each frequency interval is corresponding to a frequency detection module, and n is an integer greater than or equal to 2; obtaining a current internal clock frequency of the system, and using the current internal clock frequency as a reference clock frequency; selecting a frequency detection module corresponding to a frequency interval according to the reference clock frequency; and detecting, by the selected frequency detection module, a to-be-detected clock according to a frequency offset range of the reference clock frequency. By using the present disclosure, a risk that an internal clock of the system is attacked may be reduced, and system security may be improved.

A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.