Circuits and operating methods thereof for correcting phase errors introduced by amplifiers employing gallium nitride (GaN) transistors are described. The phase errors are caused by trapping effects exhibited by the GaN transistors. The circuits described herein pre-distort the phase of the input signal to compensate for the phase error introduced by the amplifier. Thereby, the phase of the output signal of the amplifier has a reduced phase error. For example, the output signal may have a near zero (or zero) phase error.

Provided is a bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal. The bias circuit includes: an FET that has a power supply voltage supplied to a drain thereof and that outputs the first bias current or voltage from a source thereof; a first bipolar transistor that has a collector thereof connected to a gate of the FET, that has a base thereof connected to the source of the FET, that has a common emitter and that has a constant current supplied to the collector thereof; and a first capacitor that has one end thereof connected to the collector of the first bipolar transistor and that suppresses variations in a collector voltage of the first bipolar transistor.

An apparatus, system, and method are provided for energy conversion. For example, the apparatus can include a trans-impedance node, a reactive element, and a trans-impedance circuit. The reactive element can be configured to transfer energy to the trans-impedance node. The trans-impedance circuit can be configured to receive one or more control signals and to dynamically adjust an impedance of the trans-impedance node. The trans-impedance node, as a result, can operate as an RF power switching supply based on the one or more control signals.

A method and a device for amplifying an input signal include a power amplifier for amplifying a binary input signal, a modulation device for generating the binary input signal on the basis of the input signal, the input signal being a complex-valued signal and the binary input signal being a real-valued signal, the modulation device including an adding device configured to add the complex-valued input signal to a complex-valued carrier signal of a predefined frequency and to thus generate a resulting complex-valued signal, and the modulation device including a combination device connected downstream from the adding device and configured to generate the real-valued binary input signal from the real part and the imaginary part of the resulting complex-valued signal by combining the real part and the imaginary part of the resulting complex-valued signal.

A method and a device for amplifying an input signal include a power amplifier for amplifying a binary input signal, a modulation device for generating the binary input signal on the basis of the input signal, the input signal being a complex-valued signal and the binary input signal being a real-valued signal, the modulation device including an adding device configured to add the complex-valued input signal to a complex-valued carrier signal of a predefined frequency and to thus generate a resulting complex-valued signal, and the modulation device including a combination device connected downstream from the adding device and configured to generate the real-valued binary input signal from the real part and the imaginary part of the resulting complex-valued signal by combining the real part and the imaginary part of the resulting complex-valued signal.

An apparatus for providing a supply control signal for a supply unit, the supply unit being configured to provide a variable controlled power supply to the power amplifier. The apparatus includes a determination module configured to determine a deviation of a signal from at least one nominal value; and an adjustment module configured to provide the supply control signal after an adjustment based on the determined deviation.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

Circuits, devices and methods related to antenna tuner. In some embodiments, an antenna can be tuned by amplifying a signal for transmission by operating a transistor with a base current, and monitoring the base current. The method can further include adjusting an antenna tuner to thereby adjust an antenna load impedance presented to the amplified signal, with the adjustment being based on a variation of the monitored base current.

Coupling apparatuses, circuits having such coupling apparatuses and corresponding methods are provided that involve a first and a second signal being coupled out from an out-coupling circuit part and being separately coupled into first and second circuit pmts. The use of different coupling mechanisms effects signal separation in this case. In particular, one of the signals can be coupled as a differential signal and the other as a common mode signal.