An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.

Embodiments describe systems, apparatuses, and methods for transmitting/receiving signal data to/from a plurality of transceiver modules. Devices in accordance with some embodiments can include a plurality of wireless transceiver modules, each wireless transceiver module to be communicatively coupled to a corresponding external transceiver mixture, one or more antennas to exchange signal data with the plurality of external transceiver modules, a radio frequency (RF) circulator, and one or more amplifiers to amplify the signal data received by the one or more antennas and signal data to be transmitted by the one or more antennas. The use of the RF circulator prevents transmitting signals that may collide with each other and cause interference with the communications.

An amplification circuit includes: a power supply terminal that is connected to a power supply; a transistor that has a source terminal, a drain terminal, and a gate terminal to which a high-frequency signal is input; a transistor that has a source terminal that is connected to the drain terminal, a drain terminal that outputs a high-frequency signal, and a gate terminal that is grounded; a capacitor that is serially disposed on a second path that connects the gate terminal and the power supply terminal to each other; and a switch that is serially disposed on a first path or the second path. The drain terminal and the gate terminal are connected to each other via the switch and the capacitor.

A switch control circuit a multiplexer switch circuit and a control method for a multiplexer switch control circuit are provided. The switch control circuit comprises a first control switch, a first capacitor and a field-effect transistor switch. When the first control switch is switched off, a charging voltage released by the first capacitor can control the switching-on of the field-effect transistor switch. At this moment, since the first control switch is switched off, and a power source signal cannot reach a gate electrode of the field-effect transistor switch, power source noise cannot be coupled to a line where source and drain electrodes of the field-effect transistor switch are located. Thus, in a discharge stage of the first capacitor, a discharge voltage can serve as a control signal to control the switching-on of the field-effect transistor switch.

In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

A power amplifier output stage includes a first output array group having a first plurality of semiconductor devices, and a first loading adjustment module coupled to the first output array group. The first loading adjustment module is configured to adjust a loading of the first output array group to produce a first power dissipation value associated with the first output array group. The power amplifier output stage further includes a second output array group having a second plurality of semiconductor devices, and a second source loading adjustment module coupled to a second input of the second output array. The second source loading adjustment module is configured to adjust a source loading of the second output array group to produce a second power dissipation value associated with the second output array group, the first power dissipation value being different from the second power dissipation value.

A radio-frequency circuit includes a filter circuit and a power amplifier circuit. The filter circuit includes a first pass band corresponding to a band of a cellular communication system and a second pass band corresponding to a band of a satellite communication system. The power amplifier is connected to the filter circuit. The second pass band is positioned between the first pass band and a third pass band corresponding to a band of a satellite navigation system, or the second pass band at least partially matches the first pass band.

The present disclosure relates to a transmitter system that includes a radio frequency (RF) power amplifier (PA) and a baseband processor. The RF PA is configured to amplify an RF input signal to an RF output signal and configured to receive an analog bias adjustment signal, which is applied to correct dynamic bias errors in the RF PA caused by amplification variations that have time constants. The baseband processor, in response to an input envelope and a feedback output envelope, is configured to generate a feedback envelope error signal. Herein, the input envelope is estimated based on a baseband input signal received by the baseband processor, and the feedback output envelope is estimated based on the RF output signal. The RF input signal and the analog bias adjustment signal fed to the RF PA are generated from the baseband input signal and the feedback envelope error signal, respectively.

Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

A symbol power tracking amplification system including: a modem to generate data and symbol tracking signals; a symbol tracking modulator including a control circuit, first and second voltage supply circuits and a switch circuit, the control circuit generates first and second voltage level control signals in response to the symbol tracking signal, the first voltage supply circuit generates a first output voltage in response to the first voltage level control signal, the second voltage supply circuit generates a second output voltage in response to the second voltage level control signal and the switch circuit outputs the first or second output voltages as a supply voltage in response to a switch control signal; an RF block to generate an RF signal based on the data signal from the modem; and a power amplifier to adjust a power level of the RF signal based on the supply voltage.