A fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.

Embodiments of the present disclosure include a harmonic power amplifying circuit with high efficiency and high bandwidth and a radio-frequency power amplifier. The circuit comprises an input matching network (11), a transistor (M), and an output matching network (12); a gate of the transistor (M) connected to an output end of the input matching network (11), a drain thereof connected to an input end of the output matching network (12), and a source thereof being grounded; wherein the output matching network (12) enables a lower sideband of the harmonic power amplifying circuit to work in a continuous inverse F amplification mode and an upper sideband of the harmonic power amplifying circuit to work in a continuous F amplification mode; wherein the output matching network (12) and a parasitic network of the transistor (M) form a low pass filter. By transitioning from the continuous inverse F power amplifier working mode to the continuous F power amplifier working mode, the efficiency of a continuous harmonic control power amplifier is effectively improved to be higher than 60%, a relative bandwidth is improved to be higher than 80%, and the harmonic impedance is simple to match and easy to realize.

A power amplification circuit including: a power splitter which splits an input signal into a first signal and a second signal; a first carrier amplifier which amplifies the first signal to output a first amplified signal; a first peak amplifier which amplifies the second signal when a power level of the second signal is larger than or equal to a predetermined power level to output a second amplified signal; and a combiner which combines the first amplified signal and the second amplified signal, in which the first carrier amplifier and the first peak amplifier are provided to a same semiconductor substrate.

A current control circuit controls a bias current that is supplied to an amplifier transistor that amplifies a radio-frequency signal and includes a node, a constant current source circuit that supplies a first current to the node, and a variable current source circuit that supplies a second current to the node, based on a result of comparison between a potential of the node and a reference potential. The node outputs a control current including the first current and the second current for controlling the bias current.

Wideband power combiners and splitters are provided herein. In certain embodiments, a power combiner/splitter is implemented with a first coil connecting a first port and a second port, and a second coil connecting a third port and a fourth port. The first coil and the second coil are inductively coupled to one another. For example, the first coil and the second coil can be formed using adjacent conductive layers of a semiconductor chip, an integrated passive device, or a laminate. The power combiner/splitter further includes a fifth port tapping a center of the first coil and a sixth port tapping a center of the second coil. The fifth port and the sixth port serve to connect capacitors and/or other impedance to the center of the coils to thereby provide wideband operation.

According to at least one example of the disclosure, a power amplifier system is provided comprising an amplifying transistor configured to amplify a radio frequency signal, a bias circuit configured to provide a bias voltage to the amplifying transistor, and a clamp circuit for protecting the power amplifier system by absorbing a current flowing through the amplifying transistor when the clamp circuit is switched on. The clamp circuit is connected at a bias node between the bias circuit and the amplifying transistor and includes a clamp transistor and a clamp diode, the clamp diode having one end connected to a collector of the clamp transistor at the bias node and another end connected to a base of the clamp transistor.

A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.

A digital envelop tracker for a power amplifier. The digital envelop tracker includes a supply filter for filtering a supply voltage to a power amplifier, a level selection circuitry configured to determine a level of supply voltage based on an instantaneous power of an input data stream, schedule a series of switching events based on the determined level of supply voltage, and generate a level select signal based on the scheduled series of switching events, and a switch for connecting one of supply voltages to the supply filter based on the level select signal. The level selection circuitry schedules a primary switching event of the switch based on the determined level of supply voltage and secondary switching events of the switch delayed with respect to the primary switching event based on the determined level of supply voltage to generate a filter response of the supply filter with smaller peaking.

A circuit for filtering a signal corresponding to a time of flight (TOF) of light from a laser reflected off an object to a photo detector, the circuit includes a preamplifier, a DC cancelation loop, and an AC cancelation loop. The preamplifier may be configured to receive the signal from the photo detector corresponding to an output of the laser reflected off an object remote from the laser and photo detector. The DC cancelation loop includes a current feedback DC servo loop. The AC cancelation loop includes a feedback network driven by a floating class AB output stage, and the preamplifier configured to drive the floating class AB output stage, wherein the preamplifier is driven by an error signal of the feedback network and creates an AC signal path with the feedback network and floating class AB output stage.

A power amplifier circuit includes an input-stage power amplifier configured to receive a radio-frequency input signal, an output-stage power amplifier configured to output an amplified radio-frequency output signal, and an intermediate-stage power amplifier disposed between the input-stage power amplifier and the output-stage power amplifier. The intermediate-stage power amplifier includes a first transistor, a second transistor, and a capacitor having a first end connected to an emitter of the first transistor and a second end connected to a collector of the second transistor. The intermediate-stage power amplifier receives a signal at a base of the second transistor thereof and outputs an amplified signal from a collector of the first transistor thereof.