A circuit for downlink/uplink operational mode switching in a TDD wireless communication system comprises a field-effect transistor operatively connected to a power amplifier on the downlink path of a RF front-end apparatus in a TDD wireless communication system, a first voltage generator connected to a large-value first resistor, a second voltage generator connected to a second resistor, a large-value hold capacitor, and a sample-and-hold circuit configured to be switched between a reception configuration, wherein the first voltage generator is connected to the gate of the field-effect transistor and the large-value capacitor is connected to the first voltage generator through the first resistor, and a transmission configuration, wherein the gate of the field-effect transistor is connected to the hold capacitor and the hold capacitor is connected to the second voltage generator through the second resistor.

An example apparatus includes: a folded cascode circuit including a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first feedback loop including a third output terminal, the third output terminal coupled to the first output terminal; a second feedback loop including a fourth output terminal, the fourth output terminal coupled to the second output terminal; and a first driver including a first control terminal and a fifth output terminal, the first control terminal coupled to the third output terminal; and a second driver including a second control terminal and a sixth output terminal, the second control terminal coupled to the fourth output terminal, the sixth output terminal coupled to the fifth output terminal.

In a power amplifying module in which a plurality of differential amplifying circuits is mounted on a substrate, each of the differential amplifying circuits includes a chip device that includes at least two amplifiers, each of the at least two amplifiers amplifying a differential signal, a balun that includes a primary side winding wire and a secondary side winding wire, both ends of the primary side winding wire being connected to an output of the chip device, and a capacitor provided between a power feed point of the primary side winding wire and a reference potential. In at least one of the plurality of the differential amplifying circuits, the distance from one end of the primary side winding wire to the power feed point is different from the distance from the other end of the primary side winding wire to the power feed point.

In a power amplifying module in which a plurality of differential amplifying circuits is mounted on a substrate, each of the differential amplifying circuits includes a chip device that includes at least two amplifiers, each of the at least two amplifiers amplifying a differential signal, a balun that includes a primary side winding wire and a secondary side winding wire, both ends of the primary side winding wire being connected to an output of the chip device, and a capacitor provided between a power feed point of the primary side winding wire and a reference potential. In at least one of the plurality of the differential amplifying circuits, the distance from one end of the primary side winding wire to the power feed point is different from the distance from the other end of the primary side winding wire to the power feed point.

Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

In an example, a system includes an amplifier configured to produce a bandgap voltage reference. The system also includes a current source configured to provide a current to bias the amplifier. The system includes a switching circuit configured to receive a first current replica signal and a second current replica signal, the switching circuit further configured to cause the current source to provide the current to bias the amplifier based on either the first current replica signal or the second current replica signal.

A noise filtering circuit including: an amplifier which receives a reference bias through a first input terminal, generates an amplified output voltage and outputs the amplified output voltage through an output terminal, and receives an output voltage generated on the basis of the amplified output voltage through a second input terminal; a resistance component connected between the output terminal of the amplifier and the second input terminal; and a capacitor connected to the resistance component.

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use V.sub.OFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage V.sub.OUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.