A switched capacitor modulator (SCM) includes a RF power amplifier. The RF power amplifier receives a rectified voltage and a RF drive signal and modulates an input signal in accordance with the rectified voltage to generate a RF output signal to an output terminal. A reactance in parallel with the output terminal is configured to vary in response to a control signal to vary an equivalent reactance in parallel with the output terminal. A controller generates the control signal and a commanded phase. The commanded phase controls the RF drive signal. The reactance is at least one of a capacitance or an inductance, and the capacitance or the inductance varies in accordance with the control signal.

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

Embodiments relate to a circuit implementation for extending the bandwidth of an amplifier. The extended bandwidth amplifier includes an amplifier coupled between an input node and an output node of the extended bandwidth amplifier. The amplifier has an input capacitance and an output capacitance. The extended bandwidth amplifier additionally includes a first digitally-trimmable negative-capacitance capacitor coupled between the input node of the extended bandwidth amplifier and a power supply terminal. The digitally-trimmable negative-capacitance capacitor includes a first branch, a second branch, and a controller. The first branch includes a first capacitor having a first negative capacitance, and a first switch. The second branch includes a second capacitor having a second negative capacitance, and a second switch. The controller is configured to turn on the first switch and the second switch based on the input capacitance of the amplifier.

The amplifier includes an input circuit configured to convert an input signal into a current; an output circuit comprising at least one switching element for reducing a voltage change of an output end of the input circuit and configured to provide an output signal; and a biasing circuit connected to the at least one switching element to form a feedback loop for reducing the voltage change of the output end of the input circuit.

To improve stability of a reference current in a current source circuit that generates the reference current by using capacitors. The current source circuit includes a pair of capacitors, a switching circuit, an operational amplifier, and an output transistor. The switching circuit charges one of the pair of capacitors with a predetermined charging current, and transfers electric charge from the one of the pair of capacitors to the other of the pair of capacitors. The operational amplifier amplifies a difference between the terminal voltage of the other of the pair of capacitors and a predetermined reference voltage and outputs the difference that has been amplified as an output voltage. The output transistor outputs a current corresponding to the output voltage as a reference current.

The present disclosure discloses a switched capacitor amplifier apparatus for improving level-shifting. An amplifier includes input terminals and output terminals. Two capacitor circuits correspond to signal input terminals and signal output terminals and each includes a sampling capacitor circuit, a load capacitor and a level-shifting capacitor. The sampling capacitor circuit samples an input signal from one of the signal input terminals to one of the input terminals. An electrical charge neutralizing capacitor is coupled between the output terminals. The load capacitor and the level-shifting capacitor are charged according to an output from one of the output terminals in an estimation period. The level-shifting capacitor charges the load capacitor in a level-shifting period to generate an output signal at one of the signal output terminals. The electrical charge neutralizing capacitor receives and provides electrical charges from the output terminals to the level-shifting capacitor respectively in the estimation period and the level-shifting period.

A signal detection circuit includes: a first capacitor having a first terminal connected with a first main terminal of a switching element; a second capacitor having a first terminal connected with a second main terminal of the switching element; and a detection circuit having a differential circuit configuration. The detection circuit receives, as input signals, a signal from a second terminal of the first capacitor and a signal from a second terminal of the second capacitor, detects detection target signals based on the input signals. The detection target signals include a signal of the first main terminal of the switching element and a signal of the second main terminal of the switching element.

An amplifier arrangement comprises a sensor input and a first and a second amplifier. The first amplifier has a first amplifier output and a first input connected to a first reference potential terminal and a second input connected to the sensor input in a direct fashion and to the first amplifier output via a feedback path having a switched integration capacitor that is charged by the feedback path during a first switching phase and discharged during a second switching phase. The second amplifier has a second amplifier output, a first input connected to a second reference potential terminal and a second input. A first feedback capacitor is connected in-between two pairs of feedback switches. A second feedback capacitor is connected between the second amplifier output and the second input of the second amplifier. An impedance element is coupled between the second amplifier output and the sensor input.

A chopper switch is connected appropriately to multistage amplifiers.

A semiconductor circuit includes a plurality of amplifiers that is connected in series and individually amplify and supply a signal on an input side thereof to an output side thereof. A first chopper switch is connected to an input side of a first amplifier connected first among the plurality of amplifies, and a second chopper switch is connected to an output side of the first amplifier. The first and second chopper switches act in synchronism with a first chopper clock. A third chopper switch is connected to an input side of a second amplifier connected second or later among the plurality of amplifiers, and a fourth chopper switch is connected to an output side of the second amplifier. The third and fourth chopper switches act in synchronism with a second chopper clock. A phase compensation capacitor is connected at one end thereof to an input portion of the third chopper switch.

According to an embodiment, there is provided an amplifier circuit including a first capacitive element, a first GM amplifier, and a second GM amplifier. The first GM amplifier includes a first input node, a second input node, and an output node. The output node is connected to one end of the first capacitive element. The second GM amplifier includes a first input node, a second input node, and an output node. The output node is connected to one end of the first capacitive element and the second input node.