Analog neural memory array in artificial neural network with substantially constant array source impedance with adaptive weight mapping and distributed power

Abstract

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

Claims

1. An analog neural memory system comprising: an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines; a set of dummy bit line switches arranged on a first end of the array, each of the set of dummy bit line switches coupled to one of the dummy bit lines in the plurality of dummy bitlines; a set of bit line switches arranged on a second end of the array opposite the first end of the array, each of the set of bit line switches coupled to one of the bit lines in the plurality of bit lines; and a summer for summing outputs from one or more bit lines, wherein the summer is adjustable based on a variable resistor or a variable capacitor; wherein during a read operation of a selected cell in the first plurality of columns of cells, current passes through a path formed in a bit line switch in the set of bit line switches coupled to the bit line connected to the selected cell in the first plurality of column of cells, the selected cell, a dummy bit line, and a dummy bit line switch in the set of dummy bit line switches into the summer.

2. The system of claim 1, wherein each dummy bit line switch in the set of dummy bit line switches is configured to pull the coupled dummy bit line to ground.

3. The system of claim 2, wherein array bit line interconnect impedance remains substantially constant when cells attached to the plurality of bit lines are selected for a read operation.

4. The system of claim 1, wherein two or more of the dummy bit line switches in the first set of dummy bit line switches are connected to a common ground.

5. The system of claim 1, wherein two or more of the bit lines are coupled to one another.

6. The system of claim 1, wherein array bit line interconnect impedance remains substantially constant when cells attached to the plurality of bit lines are selected for a read operation.

7. The system of claim 1, wherein the set of bit line switches couples to one or more of a sensing circuit, a summer, or an analog-to-digital converter circuit.

8. The system of claim 1, wherein the non-volatile memory cells in the array are split gate flash memory cells.

9. The system of claim 1, wherein the non-volatile memory cells in the array are stacked gate flash memory cells.

10. The system of claim 1, wherein the summer is adjustable based on a variable resistor.

11. The system of claim 1, wherein the summer is adjustable based on a variable capacitor.

12. The system of claim 1, further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.

13. The system of claim 12, wherein the analog-to-digital converter comprises a successive approximation register.

14. The system of claim 13, wherein the analog-to-digital converter is a pipelined analog-to-digital converter.

15. The system of claim 1, further comprising: a source line coupled to a source line terminal of a row of non-volatile memory cells; and a source line transistor configured to pull the source line to ground.

16. The system of claim 15, wherein array interconnect impedance remains substantially constant when cells attached to the bit lines are selected for operation.

17. The system of claim 15, wherein the bit line switches couples to one or more of a sensing circuit, a summer, or an analog-to-digital converter circuit.

18. The system of claim 15, wherein two or more of the dummy bit line switches in the set of dummy bit line switches are connected to a common ground.

19. An analog neural memory system comprising: a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines; a second array of non-volatile memory cells, the cells in the second array arranged in rows and columns, wherein a second plurality of columns of cells in the second array is connected to a different bit line in the plurality of bit lines and a second plurality of columns of cells in the second array is connected to a different dummy bit line in a plurality of dummy bitlines; and a set of multiplexors coupled to the first array and the second array and coupled to ground; wherein array interconnect impedance of the first array and the second array remain substantially constant when cells attached to the bit lines are selected for operation.

20. The system of claim 19, wherein the non-volatile memory cells in the first array and the second array are split gate flash memory cells.

21. The system of claim 19, wherein the non-volatile memory cells in the first array and the second array are stacked gate flash memory cells.

22. The system of claim 19, further comprising a summer for summing outputs from one or more bit lines.

23. The system of claim 22, wherein the summer is adjustable based on a variable resistor.

24. The system of claim 22, wherein the summer is adjustable based on a variable capacitor.

25. The system of claim 22, further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.

26. The system of claim 25, wherein the analog-to-digital converter comprises a successive approximation register.

27. The system of claim 26, wherein the analog-to-digital converter is a pipelined analog-to-digital converter.

28. A method of operating an analog neural memory system comprising a first array comprising non-volatile memory cells arranged in rows and columns, a second array comprising non-volatile memory cells arranged in rows and columns, column multiplexors, local bit lines, and global bit lines, the method comprising: selecting, by the column multiplexors, a local bit line of the first array or a local bit line of the second array, and coupling the selected bit line to a global bit line; and multiplexing the global bit line with a second global bit line adjacent to the global bit line.

29. The method of claim 28, further comprising: summing outputs from one or more global bit lines.

30. A method of operating an analog neural memory system comprising an array of non-volatile memory cells, the method comprising: receiving, by a first n-bit analog-to-digital converter, a first output from the array; receiving, by a second n-bit analog-to-digital converter, a second output from the array; combining the first n-bit analog-to-digital converter with the second n-bit analog-to-digital converter to form a third analog-to-digital converter that generates a third output based on the first output and the second output, wherein the third output has a precision greater than n bits.

31. The method of claim 30, wherein the first analog-to-digital converter is a serial analog-to-digital converter and the second analog-to-digital converter is a serial analog-to-digital converter.

32. The method of claim 30, wherein the first analog-to-digital converter is a successive approximation converter and the second analog-to-digital converter is a successive approximation converter.

33. An analog neural memory system comprising: an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a bit line in a plurality of bitlines, and weights of a neural network are distributed among the bitlines to maintain voltage drop or power consumption at a substantially equal level among the bitlines.

34. The system of claim 33, wherein the non-volatile memory cells in the array are split gate flash memory cells.

35. The system of claim 33, wherein the non-volatile memory cells in the array are stacked gate flash memory cells.

36. The system of claim 33, further comprising a summer for summing outputs from one or more bit lines.

37. The system of claim 36, wherein the summer is adjustable based on a variable resistor.

38. The system of claim 36, wherein the summer is adjustable based on a variable capacitor.

39. The system of claim 36, further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.

40. The system of claim 39, wherein the analog-to-digital converter comprises a successive approximation register.

41. The system of claim 40, wherein the analog-to-digital converter is a pipelined analog-to-digital converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 depicts a prior art artificial neural network.

(2) FIG. 2 depicts a prior art split gate flash memory cell.

(3) FIG. 3 depicts another prior art split gate flash memory cell

(4) FIG. 4 depicts another prior art split gate flash memory cell.

(5) FIG. 5 depicts another prior art split gate flash memory cell.

(6) FIG. 6 depicts another prior art split gate flash memory cell.

(7) FIG. 7 depicts a prior art stacked gate flash memory cell.

(8) FIG. 8 depicts a twin split-gate memory cell.

(9) FIG. 9 depicts different levels of an exemplary artificial neural network utilizing one or more VMM arrays.

(10) FIG. 10 depicts a VMM system comprising a VMM array and other circuitry.

(11) FIG. 11 depicts an exemplary artificial neural network utilizing one or more VMM systems.

(12) FIG. 12 depicts an embodiment of a VMM array.

(13) FIG. 13 depicts another embodiment of a VMM array.

(14) FIG. 14 depicts another embodiment of a VMM array.

(15) FIG. 15 depicts another embodiment of a VMM array.

(16) FIG. 16 depicts another embodiment of a VMM array.

(17) FIG. 17 depicts a VMM system.

(18) FIGS. 18A, 18B, and 18C depict a prior art VMM array.

(19) FIGS. 19A, 19B, and 19C depicts an improved VMM array.

(20) FIG. 20 depicts another improved VMM array.

(21) FIGS. 21A and 21B depicts another improved VMM arrays.

(22) FIG. 22 depicts another improved VMM array comprising a redundant array.

(23) FIG. 23 depict another improved VMM system that comprises two VMM arrays and shared dummy bit line switching circuitry.

(24) FIG. 24 depicts another improved VMM system.

(25) FIG. 25 depicts an embodiment of a summer circuit.

(26) FIG. 26 depicts another embodiment of a summer circuit.

(27) FIG. 27A depicts another embodiment of a summer circuit.

(28) FIG. 27B depicts another embodiment of a summer circuit.

(29) FIG. 28A depicts an embodiment of an output circuit.

(30) FIG. 28B depicts another embodiment of an output circuit.

(31) FIG. 28C depicts another embodiment of an output circuit.

(32) FIG. 29 depicts a neuron output circuit.

(33) FIG. 30 depicts an embodiment of an analog-to-digital converter.

(34) FIG. 31 depicts another embodiment of an analog-to-digital converter.

(35) FIG. 32 depicts another embodiment of an analog-to-digital converter.

(36) FIG. 33 depicts another embodiment of an analog-to-digital converter

DETAILED DESCRIPTION OF THE INVENTION

(37) The artificial neural networks of the present invention utilize a combination of CMOS technology and non-volatile memory arrays.

(38) Embodiments of Improved VMM Systems

(39) FIG. 17 depicts a block diagram of VMM system 1700. VMM system 1700 comprises VMM array 1701, row decoders 1702, high voltage decoders 1703, column decoders 1704, bit line drivers 1705, input circuit 1706, output circuit 1707, control logic 1708, and bias generator 1709. VMM system 1700 further comprises high voltage generation block 1710, which comprises charge pump 1711, charge pump regulator 1712, and high voltage level generator 1713. VMM system 1700 further comprises algorithm controller 1714, analog circuitry 1715, control logic 1716, and test control logic 1717. The systems and methods described below can be implemented in VMM system 1700.

(40) Input circuit 1706 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter), DTC (digital to time converter), AAC (analog to analog converter, such as current to voltage converter), PAC (pulse to analog level converter), or any other type of converters. Input circuit 1706 may implement normalization, scaling functions, or arithmetic functions. Input circuit 1706 may implement a temperature compensation function on the input such as modulate the output voltage/current/time/pulse(s) as a function of temperature. Input circuit 1706 may implement activation function such as ReLU or sigmoid.

(41) Output circuit 1707 may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as current to voltage converter), ATC (analog to time converter), APC (analog to pulse(s) converter), or any other type of converter. Output circuit 1707 may implement activation function such as ReLU or sigmoid. Output circuit 1707 may implement statistic normalization, regularization, up/down scaling functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) on the neuron outputs, which are the outputs of VMM array 1701. Output circuit 1707 may implement a temperature compensation function on the neuron outputs (such as voltage/current/time/pulse(s)) or array outputs (such as bitline outputs) such as to keep power consumption of the VMM array 1701 approximately constant or to improve precision of the VMM array 1701 (neuron) outputs such as by keeping the slope approximately the same.

(42) FIG. 18A depicts prior art VMM system 1800. VMM system 1800 comprises exemplary cells 1801 and 1802, exemplary bit line switch 1803a, 1803b, 1803c, 1803d (which connects bit lines to sensing circuitry), exemplary dummy bit line switch 1804a, 1804b, 1804c, 1004d (which couples to a low bias level such as ground (or near ground) level in read), and exemplary dummy cells 1805 and 1806 (source line pull down cells). Bit line switch 1803a is coupled to a column of cells, including cells 1801 and 1802, that are used to store data in VMM system 1800. Dummy bit line switch 1804a, 1804b, 1804c, 1804 are each coupled to a column (bitline) of cells that are dummy cells are not used to store data in VMM system 1800. This dummy bitline, which can also be referred to as a source line pulldown bitline, is used as a source line pull down during read operations, meaning that it is used to pull the source line to a low bias level, such as ground (or near ground), through the dummy cells in the dummy bitline. It is to be noted that dummy bit line switch 1804a, 1804b, 1804c, 1804 and bit line switch 1803a, 1803b, 1803c, 1803d both appear on the same end of the array, i.e. they all appear at a common end of the column of cells to which they coupled, and are thus are arrayed in a single row.

(43) One drawback of VMM system 1800 is that the input impedance for each cell varies greatly due to the length of the electrical path through the relevant bit line switch, the cell itself, and the relevant dummy bit line switch. For example, FIG. 18B shows the electrical path through bit line switch 1803, cell 1801, dummy cell 1805, and dummy bit line switch 1804. Similarly, FIG. 18C shows the electrical path through bit line switch 1803, vertical metal bitline 1807, cell 1802, dummy cell 1806, vertical metal bitline 1808, and dummy bit line switch 1804. As can be seen, the path through cell 1802 traverses a significantly larger length of bit line and dummy bit line, which is associated with a higher capacitance and higher resistance. This results in cell 1802 having a greater parasitic impedance in the bit line or source line than cell 1801 in FIG. 18B. This variability is a drawback, for instance, because it results in a variance in the precision of the cell output as applied to read or verify (for program/erase tuning cycles) cells depending on their location within the array.

(44) FIG. 19A depicts VMM system 1900, which improves upon prior art VMM system 1800. VMM system 1900 comprises exemplary cells 1901 and 1902; exemplary bit line switches 1903a, 1903b, 1903c, and 1903d, which connect the bit lines to sensing circuitry; exemplary dummy cells 1905 and 1906, which can serve as source line pull down cells; and exemplary dummy bit line switches 1904a, 1904b, 1904c, and 1904d. As an example, one end of dummy bit line switch 1904a connects to a low voltage level, such as ground, during a read operation, and the other end connects to dummy cells 1905 and 1906 that are used as a source line pull down. As can be seen, exemplary dummy bit line switch 1904a and the other dummy bit line switches are located on the opposite end of the array from bit line switch 1903a and the other bit line switches.

(45) The benefit of this design can be seen in FIGS. 19B and 19C. In FIG. 19B, cell 1901 is selected for reading, and in FIG. 19C, cell 1902 is selected for reading.

(46) FIG. 19B depicts the electrical path through bit line switch 1903, cell 1901, dummy cell 1905 (source line pull down cell), vertical metal bit line 1908, and dummy bit line switch 1904 (which couples to a low level such as ground during a read operation). FIG. 19C depicts the electrical path through bit line switch 1903, vertical metal line 1907, cell 1902, dummy cell 1906 (source line pull down cell), and dummy bit line switch 1904. The paths are substantially the same in terms of interconnect length, which is true for all cells in VMM system 1900. As a result, the impedance of the bit line impedance plus source line impedance of each cell is substantially the same, which means that the variance in the amount of parasitic voltage drop drawn during a read or verify operation of each cell in the array is substantially the same.

(47) FIG. 20 depicts VMM system 2000 with a global source line pulldown bitline. VMM system 2000 is similar to VMM system 1900, except that: the dummy bit lines 2005a-2005n or 2007a-2007n are connected together (to act as global source line pulldown line to pull memory cell source lines to ground level during read or verify); the dummy bit line switches, such as dummy bit line switch 2001 and 2002, are connected or coupled to a common ground, labeled ARYGND (array ground); and the source lines are coupled together to source line switch 2004, which selectively pulls the source lines to ground. These changes further decrease the variance in parasitic impedance for each cell in the array during a read or verify operation.

(48) In an alternative embodiment, one or more dummy bit lines and one or more dummy bit line switches can be used instead of source line switch 2004 to pull the source lines to ground.

(49) In another embodiment, dummy rows can be utilized between rows as physical barriers to avoid FG-FG coupling (of two adjacent cells) between rows.

(50) FIG. 21A depicts VMM system 2100. In some embodiments, the weights, W, stored in a VMM are stored as differential pairs, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 2100, half of the bit lines are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W− lines, that is, bit lines connecting to memory cells implementing negative weights W−. The W− lines are interspersed among the W+ lines in an alternating fashion. The subtraction operation is performed by a summation circuit that receives current from a W+ line and a W− line, such as summation circuits 2101 and 2102. The output of a W+ line and the output of a W− line are combined together to give effectively W=W+−W− for each pair of (W+, W−) cells for all pairs of (W+, W−) lines. Optionally, dummy bitlines and source line pulldown bitlines, such as those shown in FIGS. 19 and 20, can be used in VMM system 2100 to avoid FG-FG coupling (of two adjacent cells) and/or to reduce IR voltage drop in the source line during a read or verify operation.

(51) FIG. 21B depicts another embodiment. In VMM system 2110, positive weights W+ are implemented in first array 2111 and negative weights W− are implemented in a second array 2112, separate from the first array, and the resulting weights are appropriately combined together by summation circuits 2113. Optionally, dummy bitlines and source line pulldown bitlines, such as those shown in FIGS. 19 and 20, can be used in VMM system 2110 to avoid FG-FG coupling and/or to reduce IR voltage drop in the source line during a read or verify operation.

(52) VMM systems can be designed such that W+ and W− pairs are placed within the array in a manner that reduces FG to FG coupling or distributes power consumption in a more even fashion across the array and the output circuits. This is described below with reference to Tables 10 and 11. Additional details regarding the FG to FG coupling phenomena are found in U.S. Provisional Patent Application No. 62/981,757, filed on Feb. 26, 2020 by the same assignee, and titled “Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network,” which is incorporated by reference herein.

(53) Table 10A shows an exemplary physical layout of an arrangement of two pairs of (W+, W−) bit lines. One pair is BL0 and BL1, and a second pair is BL2 and BL3. In this example, 4 rows are coupled to source line pulldown bit line BLPWDN. BLPWDN is placed between each pair of (W+, W−) bit lines to prevent coupling (e.g., FG to FG coupling) between one pair of (W+, W−) bit lines with another pair of (W+, W−) bit lines. BLPWDN therefore serves as a physical barrier between pairs of (W+, W−) bit lines.

(54) TABLE-US-00010 TABLE 10A Exemplary Layout for W, W− Pairs BLPWDN BL0 BL1 BLPWDN BL2 BL3 BLPWDN row0 W01+ W01− W02+ W02− row1 W11+ W11− W12+ W12− row2 W21+ W21− W22+ W22− row3 W31+ W31− W32+ W32−

(55) Table 10B shows different exemplary weight combination. A ‘1’ means that the cell is used and has a real output value, and a ‘0’ means the cell is not used and has no value or no significant output value.

(56) TABLE-US-00011 TABLE 10B Exemplary Weight Combinations for W+, W− Pairs BLPWDN BL0 BL1 BLPWDN BL2 BL3 BLPWDN row0 1 0 1 0 row1 0 1 0 1 row2 0 1 1 0 row3 1 1 1 1

(57) Table 11A shows another array embodiment of a physical arrangement of (w+, w−) pair lines BL0/1 and BL2/3. The array includes redundant lines BL01 and BL23 and source line pulldown bit lines BLPWDN. Redundant bitline BL01 is used to re-map values from the pair BL0/1, and redundant bit line BL23 is used to re-map values from the pair BL2/3, which will be shown in later Tables.

(58) TABLE-US-00012 TABLE 11A Exemplary Layout for W+, W− Pairs BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 W01+ W01− W02+ W02− row1 W11+ W11− W12+ W12− row2 W21+ W21− W22+ W22− row3 W31+ W31− W32+ W32−

(59) Table 11B shows an example where the distributed weight values do not need re-mapping, basically there is no adjacent ‘1’ between adjacent bit lines.

(60) TABLE-US-00013 TABLE 11B Exemplary Weight Combinations for W+, W− Pairs BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 1 0 1 0 row1 0 1 0 1 row2 1 0 1 0 row3 0 1 0 1

(61) Table 11C shows an example where distributed weights needs to be re-mapped. Here, there are adjacent ‘1’s in BL1 and BL3, which causes adjacent bit line coupling. The values therefore are re-mapped as shown in Table 11D, resulting in no adjacent ‘1’ values between any adjacent bit lines. In addition, by re-mapping, the total current along the bit line is now reduced, which leads to a more precise value in that bit line, which also leads to more distributed power consumption along the bit lines. Optionally, additional bitlines (BL01, BL23) optionally can be used to act as redundant columns.

(62) TABLE-US-00014 TABLE 11C Exemplary Weight Combinations for w+, w− Pairs BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 0 1 1 0 row1 0 1 1 0 row2 0 1 1 0 row3 0 1 1 0

(63) TABLE-US-00015 TABLE 11D Remapped Weight Combinations for w+, w− Pairs BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 0 0 1 0 0 1 row1 1 0 0 1 0 0 row2 0 0 1 0 0 1 row3 1 0 0 1 0 0

(64) Tables 11E and 11F depict another embodiments of remapping noisy cells (or defective cells) into the redundant columns such as BL01, BL23 in Table 11E or BL0B and BL1B in Table 11F.

(65) TABLE-US-00016 TABLE 11E Remapped Weight Combinations for w+, w− Pairs BLPWDN BL01 BL0 BL1 BL2 BL3 BL23 BLPWDN row0 0 0 1 0 0 1 row1 1 0 noisy or 1 0 0 defective cell (not used) row2 0 0 1 noisy or 0 1 defective cell (not used) row3 1 0 0 1 0 0

(66) TABLE-US-00017 TABLE 11F Remapped Weight Combinations for w+, w− Pairs BLPWDN BL0A BL0B BL1A BL1B BLPWDN row0 1 0 0 0 row1 noisy or 1 1 0 defective cell (not used) row2 1 0 noisy or 1 defective cell (not used) row3 0 0 1 0

(67) Table 11G shows an embodiment of a physical arrangement of an array that is suitable for FIG. 21B. Since each bitline has either a positive weight or a negative weight, a dummy bitline acting as source line pull down or a real dummy bitline (not used, e.g., deeply or partially programmed or partially erased) and physical barrier to avoid FG-FG coupling is needed for each bit line.

(68) TABLE-US-00018 TABLE 11G Exemplary Layout for w+, w− Pairs BLPWDN BL0 BLPWDN BL1 BLPWDN row0 W01+/− W02+/− row1 W11+/− W12+/− row2 W21+/− W22+/− row3 W31+/− W32+/−

(69) In Tables 10A-10B and 11A-11G, source line pulldown bit line BLPWDN can be implemented as a real dummy bitline BLDUM or as isolation bitlines BLISO, meaning these bitlines serve to isolate the data bitlines from each other so FG-FG coupling of adjacent cells is avoided. These bitlines are not used so they are tuned (programmed or erased) to a state that does not cause FG-FG coupling or leave them vulnerable to being disturbed by other cells being tuned (either programmed or erased) in the same row or the same sector, e.g., deeply or partially programmed cells or partially erased cells so that FG voltage is at a low level state.

(70) In another embodiment, a tuning bit line coupled to a column of cells is adjacent to a target bitline coupled to a column of cells, and the tuning bit line cells are used to tune the target bitline cells to desired target values during a programming operation using the FG-FG coupling between adjacent cells. Optionally, a source line pull down bitline can be used on the side of the target bit line opposite the side adjacent to the tuning bitline.

(71) Alterative embodiments for mapping noisy or defective cells can be implemented where such cells are designated as non-used cells, meaning they are to be (deeply) programed to not contribute any value to the neuron output.

(72) Alternative embodiments for identifying fast cells (which are cells that can be programmed to reach a certain value faster than a typical cell) can be implemented, where fast cells are identified and undergo a more precise tuning algorithm to not overshoot the target during a programming operation.

(73) FIG. 22 depicts VMM system 2200. VMM system 2200 comprises redundant array 2201 that can be included in any of the VMM arrays discussed thus far. Redundant array 2201 can be used as redundancy to replace defective columns if any of the columns attached to bit line switches are deemed defective. The redundant array can have its own redundant array (neuron) outputs (e.g., bit lines), and/or redundant write and verify circuits, and/or ADC circuits for redundancy purpose. For example, when redundancy is needed, the output of the redundant ADC will replace the output of the ADC of the bad bit line. Redundant array 2201 can also be used for weight mapping such as described in Tables 10A and 10B to achieve a relatively even power distribution among bit lines.

(74) FIG. 23 depicts VMM system 2300, which comprises array 2301, array 2302, column multiplexors 2303, local bit lines LBL 2305a-d, global bit lines GBL 2308 and 2309, and dummy bit line switches 2305a-2305d. The column multiplexors 2303 are used to select the respective top local bit line 2305 of the array 2301 or bottom local bit line 2305 of the array 2302 into the global bit line 2308. In one embodiment, the (metal) global bit line 2308 has the same number of lines as number of the local bit lines, e.g. 8 or 16. In another embodiment, the global bit line 2308 has only one (metal) line per N number of local bit lines, such as one global bit line per 8 or 16 local bit lines. The column multiplexors 2303 can multiplex an adjacent global bit line (such as GBL 2309) into a global bit line of interest (such as GBL 2308) to effectively increase the width of the current global bit line. This reduces the voltage drop across the global bit line of interest (GBL 2308).

(75) Various output circuits will now be described that can be used with any of the VMM systems described herein.

(76) FIG. 24 depicts VMM system 2400. VMM system 2400 comprises array 2410; shift registers (SRs) 2401; digital-to-analog converters (DAC) 2402, which receives the input from the SRs 2401 and output an equivalent (analog or pseudo-analog) level or information (e.g., voltage/timing); summer circuits 2403; analog-to-digital converters (ADC) 2404; and bit line switches (not shown). Dummy bit lines and dummy bit line switches are present but not shown. As shown, ADC circuits can be combined together to create a single ADC with greater precision (i.e., greater number of bits).

(77) Summer circuits 2403 can include the circuits that are shown in FIGS. 25-27. It may include circuits for normalization, scaling, arithmetic operations (e.g., addition, subtraction), activation, or statistical rounding, without limitation.

(78) FIG. 25 depicts current-to-voltage summer circuit 2500 adjustable by a variable resistor, which comprises current source 2501-1, . . . , 2501-n drawing current Ineu(1), Ineu(n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier 2502, variable holding capacitor 2504, and variable resistor 2503. Operational amplifier 2502 outputs a voltage, Vneuout=R2503*(Ineu(1)+ . . . +Ineu(n)), which is proportional to the sum of the currents Ineu(1), . . . , Ineu(n). The holding capacitor 2504 is used to hold the output voltage when switch 2506 is open. This holding output voltage is used, for example, for conversion into digital bits by an ADC circuit.

(79) FIG. 26 depicts current-to-voltage summer circuit 2600 adjustable by a variable capacitor (basically an integrator), which comprises current source 2601-1, . . . , 2601-n drawing current Ineu(1), Ineu (n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier 2602, variable capacitor 2603, and switch 2604. Operational amplifier 2602 outputs a voltage, Vneuout 2605=(Ineu(1)+, . . . , +Ineu(n))*integration time/C2603, which is proportional to the sum of the currents Ineu(1), . . . , Ineu(n).

(80) FIG. 27A depicts voltage summer 2700 adjustable by variable capacitors (i.e., a switch cap SC circuit), which comprises switches 2701 and 2702, variable capacitors 2703 and 2704, operational amplifier 2705, variable capacitor 2706, and switch 512707. When switch 2701 is closed, input Vin0 is provided to operational amplifier 2705. When switch 2702 is closed, input Vin1 is provided to operational amplifier 2705. Optionally, switches 2701 and 2702 are not closed at the same time. Operational amplifier 2705 generates an output Vout, that is an amplified version of the input (either Vin0 and/or Vin1, depending on which switch is closed among switches 2701 and 2702). That is Vout=Cin/Cout*(Vin), Cin is C2703 or C2704, Cout is C2706. For example Vout=Cin/Cout*Σ(Vinx), Cin=C2703=C2704, where Vinx can be either Vin0 or Vin1. In one embodiment, Vin0 is a W+ voltage and Vin1 is a W− voltage, and voltage summer 2700 adds them together (W+−W−, by enabling appropriately polarity of the switches) to generate output voltage Vout.

(81) FIG. 27B depicts voltage summer 2750, which comprises switches 2751 (S1), 2752 (S3), 2753 (S2) and 2754 (S4), variable input capacitor 2758, operational amplifier 2755, variable feedback capacitor 2756, and switch 2757 (S5). In one embodiment, Vin0 is a W+ voltage and Vin1 is a W− voltage, and voltage summer 2750 adds them together to generate output voltage Vout (W+−W−, by enabling appropriately polarity of the switches).

(82) For Input=Vin0: when switch 2754 and 2751 are closed and switches 2753, 2752 and 2757 are opened, input Vin0 is provided to top terminal of the capacitor 2758, whose bottom terminal is connected to VREF. Then switch 2751 is open and switch 2753 is closed to transfer the charge from the capacitor 2758 into the feedback capacitor 2756. Basically then the output VOUT=(C2758/C2756)*Vin0 (for case of with VREF=0 as example).

(83) For Input=Vin1: when switches 2753, 2754, and 2757 are closed and switches 2751, 2752 and 2757 are opened, both terminals of the capacitor 2758 are discharged to VREF. Then switch 2754 is opened and switch 2752 is closed, charging the bottom terminal of the capacitor 2758 to Vin1, which in turn charges up the feedback capacitor 2756 to VOUT=−(C2758/C2756)*Vin1 (for case of VREF=0).

(84) Hence, if the sequence described above for Vin1 input is implemented after the sequence described above for Vin0 is implemented, VOUT=(C2758/C2756)*(Vin 0−Vin1), for case of VREF=0 as example. This is used for example to realize W=W+−W−.

(85) Each ADC as shown in FIG. 27 can be configured to combine with next ADC for higher bit implementation with appropriate design of the ADC.

(86) With reference again to FIG. 17, inputs to and outputs from the VMM array 1701 can be in digital or analog form. For example: Sequential Inputs IN [0:q] to DACs: In one embodiment, input circuit 1706 receives digital inputs in sequence, starting from IN0, then IN1, . . . , then INq. All input bits have the same VCGin. The input bits are provided to a DAC, which then applies analog signals as inputs to VMM array 1701. All bit line (neuron) outputs are summed with an adjusting binary index multiplier, either before an ADC or after an ADC. In another embodiment, an adjusting neuron (bit line) binary index multiplier method is used. As shown in FIG. 20, the example summer has two bit lines BL0 and Bln. A weight is distributed across multiple bit lines BL0 to BLn. For example there are 4 bit lines BL0,BL1,BL2,BL3. The output from bitline BL0 is to be multiplied by 2{circumflex over ( )}0=1. The output from bit line BLn, which stand for nth binary bit position, is multiplied by 2{circumflex over ( )}n, for example 2{circumflex over ( )}3=8 for n=3. Then the output from all bit lines after being multiplied appropriately by binary bit position 2{circumflex over ( )}n, are summed together. Then this is digitized by the ADC. This method means all cells have only a binary range, the multi level range (n-bit) is accomplished by the peripheral circuit (meaning by the summer circuit). Hence the voltage drop for all the bit lines is approximately the same for highest bias level of memory cell. In another embodiment, digital inputs IN0, IN1, . . . , then INq are applied in sequential fashion. Each input bit has a corresponding analog value VCGin. All neuron outputs are summed for all input bit evaluations, either before ADC or after ADC. Parallel Inputs to DACs: In another embodiment, inputs IN0, . . . INq are provided in parallel fashion to DACs. Each input IN[0:q] has a corresponding analog value VCGin. All neuron outputs are summed with adjusting binary index multiplier method, either before an ADC or after an ADC.

(87) In the embodiments that involve sequential operation of the arrays, power is more evenly distributed.

(88) In the embodiments that utilize the neuron (bit line) binary index method, power consumption is reduced in in the array since each cell coupled to the bit line only contains binary levels, the 2{circumflex over ( )}n level is accomplished by the summer circuit.

(89) FIGS. 28A, 28B, and 28C depict output circuits that can be used for summer circuits 2403 and analog-to-digital converters 2404 in FIG. 24.

(90) FIG. 28A depicts output circuit 2800, which comprises analog-to-digital converter 2802, which receives neuron output 2801 and outputs output digital bits 2803.

(91) FIG. 28B depicts output circuit 2810, which comprises neuron output circuit 2811 and analog-to-digital converter 2812, which together receive neuron output 2801 and generates outputs 2813.

(92) FIG. 28C depicts output circuit 2820, which comprises neuron output circuit 2821 and converter 2822, which together receive neuron output 2801 and generates outputs 2823.

(93) Neuron output circuit 2811 or 2821 can, for example, perform summing, scaling, normalization, or arithmetic operations, without limitation. Converter 2822, for example, can perform ADC, PDC, AAC, or APC operation, without limitation.

(94) FIG. 29 depicts neuron output circuit 2900, which comprises adjustable (scaling) current source 2901 and adjustable (scaling) current source 2902, which together generate output iouT, which is the neuron output. This circuit can perform a summation of a positive weight, W+, and a negative weight, W−, i.e., W=W+−W−, and up or down scaling of the output neuron current (through adjustment of the adjustable current sources 2901 and 2902) at the same time. That is, I.sub.W+ is a scaled version of W+, and I.sub.W− is a scaled version of W−.

(95) FIG. 30 depicts configurable serial analog-to-digital converter 3000. It includes integrator 3070 which integrates the neuron output current into the integrating capacitor 3002 (Cint).

(96) In one embodiment, VRAMP 3050 is provided to the inverting input of comparator 3004. The digital output (count value) 3021 is produced by ramping VRAMP 3050 until the comparator 3004 switches polarity, with counter 3020 counting clock pulses from the beginning of the ramp.

(97) In another embodiment, VREF 3055 is provided to the inverting input of comparator 3004. VC 3010 is ramped down by ramp current 3051 (IREF) until VOUT 3003 reaches VREF 3055, at which point the EC 3005 signal disables the count of counter 3020. The (n-bit) ADC 3000 is configurable to have a lower precision (fewer than n bits) or a higher precision (more than n bits), depending on the target application. The configurability of precision is done by configuring the capacitance of capacitor 3002, the current 3051 (IREF), the ramping rate of VRAMP 3050, or the clocking frequency of clock 3041, without limitation.

(98) In another embodiment, the ADC circuit of a VMM array is configured to have a precision lower than n bits and the ADC circuits of another VMM array is configured to have high a precision greater than bits.

(99) In another embodiment, one instance of serial ADC circuit 3000 of one neuron circuit is configured to combine with another instance of serial ADC circuit 3000 of the next neuron circuit to produce an ADC circuit with higher than n-bit precision, such as by combining the integrating capacitor 3002 of the two instances of serial ADC circuits 3000.

(100) FIG. 31 depicts a configurable neuron SAR (successive approximation register) analog-to-digital converter 3100. This circuit is a successive approximation converter that bases on charge redistribution using binary capacitors. It includes a binary CDAC (DAC basing on capacitors) 3101, op-amp/comparator 3102, and SAR logic and register 3103. As shown GndV 3104 is a low voltage reference level, for example ground level. SAR logic and register 3103 provides digital outputs 3106.

(101) FIG. 32 depicts a configurable neuron combo SAR analog-to-digital converter circuit 3200. This circuit combines two n-bit ADCs from two neuron circuits into one to achieve higher precision than n-bits, for example for a 4-bit ADC for one neuron circuit, this circuit can achieve>4-bit precision such as 8-bit ADC precision by combining two 4-bit ADCs. The combo circuit topology is equivalent to a split cap (bridge-capacitor (cap) or attention cap) SAR ADC circuit, for example a 8-bit 4C-4C SAR ADC resulted by combining two adjacent 4-bit 4C SAR ADC circuits. A bridge circuit 3204 (Csplit) is used to accomplish this, the capacitance of this circuit is=(total number of CDAC cap unit/total number of CDAC cap unit−1).

(102) FIG. 33 depicts a pipelined SAR ADC circuit 3300 that can be used to combine with the next SAR ADC to increase the number of bits in a pipelined fashion. SAR ADC circuit 3300 comprises binary CDAC (DAC basing on capacitors) 3301, op-amp/comparator 3302, op-amp/comparator 3303, SAR logic and register 3304. As shown GndV 3104 is a low voltage reference level, for example ground level. SAR logic and register 3103 provides digital outputs 3106. Vin is in the input voltage, VREF is a reference voltage, and GndV is a ground voltage. Vresidue is generated by capacitor 3305 and is provided as an input to the next stage of an SAR ADC.

(103) Additional implementation details regarding configurable output neurons (such as configurable neuron ADC) circuits can be found in U.S. patent application Ser. No. 16/449,201, filed on Jun. 21, 2019 by the same assignee, and titled “Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in a Deep Learning Artificial Neural Network,” which is incorporated by reference herein.

(104) It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.