An amplifier includes an amplification circuit including an input circuit receiving an input signal and configured to output an output signal by amplifying the input signal; and an offset cancelling circuit configured to cancel offset by controlling the input circuit according to activation control signal and offset control signal, wherein the offset cancelling circuit cancels the offset according to the offset control signal after the activation control signal is activated.

Technologies are provided for adaptive control of bias settings in a digital microphone. In some embodiments, a device includes a first component that provides data indicative of a clock frequency of operation in a functional mode of a digital microphone. The clock frequency clocks one or more microphone components having switching activity. The device also can include a second component that determines, using the clock frequency, an amount of bias current to supply to at least a first microphone component of the one or more microphone components. The device can further include a memory device that retains control parameters that include at least one of a first subset of parameters defining a relationship between current and frequency and a second subset of parameters defining a quantization of the relationship. The quantization including multiple bias current levels for respective frequency intervals.

A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

An amplifier circuit includes a low noise amplifier disposed in an amplification path, switches connected in series to a bypass path bypassing the low noise amplifier, a capacitor having at least one end connected between the switches in the bypass path, and a switch connected between the bypass path and a ground. The switch connected between the bypass path and the ground is connected between the other switches.

Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

A wideband amplifier includes an input matching network for matching a transconductor stage to an input impedance and includes an output matching network for matching the transconductor stage to an output impedance. Both the input and output matching networks each includes a parallel LC tank circuit arranged in parallel with a series LC tank circuit. The tank circuit arrangements configure the input and output matching networks to be resonant at a first frequency, a midrange frequency that is greater than the first frequency, and a second frequency that is greater than the midrange frequency to provide wideband matching.

A switched capacitor modulator (SCM) includes a RF power amplifier. The RF power amplifier receives a rectified voltage and a RF drive signal and modulates an input signal in accordance with the rectified voltage to generate a RF output signal to an output terminal. A reactance in parallel with the output terminal is configured to vary in response to a control signal to vary an equivalent reactance in parallel with the output terminal. A controller generates the control signal and a commanded phase. The commanded phase controls the RF drive signal. The reactance is at least one of a capacitance or an inductance, and the capacitance or the inductance varies in accordance with the control signal.

A semiconductor device including an amplifier with improved accuracy is provided. The semiconductor device includes a switch, a capacitor, a chopping circuit, and the amplifier. The amplifier includes a non-inverting input terminal, an inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The semiconductor device, with use of the switch and the capacitor, has a function of sampling and holding a first potential and a second potential input in a first period. The chopping circuit is provided on each of the input terminal side and the output terminal side of the amplifier, and the first potential and the second potential are each input to either one of the non-inverting input terminal and the inverting input terminal in a second period. In a third period, the first potential and the second potential are each input to either one of the non-inverting input terminal and the inverted input terminal, which is different from the second period. In a similar manner, the inverting output terminal and non-inverting output terminal are replaced by the chopping circuit in the second period and the third period to be output from the semiconductor device.

A reference voltage generating circuit includes a bandgap reference (BGR) circuit configured to output an active reference voltage at a first node according to a sample signal; a first charging circuit configured to charge a first capacitor using the active reference voltage according to the sample signal; a second charging circuit configured to charge a second capacitor using the active reference voltage according to the sample signal; and a comparing circuit configured to compare a voltage difference between a charge voltage of the first capacitor and a charge voltage of the second capacitor with a threshold value, wherein the sample signal is a pulse signal generated using an output of the comparing circuit and the charge voltage of the first capacitor is provided as a low power reference voltage in a low power operation mode.

An apparatus includes a differential current-to-voltage conversion circuit that includes an input sampling stage circuit, a differential integration and DC signal cancellation stage circuit, and an amplification and accumulator stage circuit. An input common mode voltage of the differential current-to-voltage circuit is independent of an output common mode voltage of the differential current-to-voltage circuit.