Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

A dynamic comparator includes a differential amplifier stage, a switching unit and a switching charge storage unit. The switching charge storage unit includes a plurality of switching transistors, and a charge storage capacitor electrically connected to the plurality of switching transistors. When an operational mode of the dynamic comparator is switched from a comparison state to a reset state, a voltage on one of a first terminal and a second terminal of the charge storage capacitor is increased from a half of the system voltage to a system voltage, so as to implement a charge recycle effect. The dynamic comparator of the present invention can have lower power consumption and lower charge-discharge current.

Amplifying circuitry configured such that when a detection circuit detects an abnormal state in which the level of signals input to a main amplifying circuit exceeds a normal range, a control circuit sets the state of integration of signals in the integration circuit to a default state. When the detection circuit detects the abnormal state and then detects that an operating state returns to a normal state in which the level of signals input to the main amplifying circuit is included in the normal range, the control circuit cancels the setting of the default state in the integration circuit.

An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

System and apparatus for measuring biopotential and implementation thereof. A device for mitigating electromagnetic interference (EMI) thereby increasing signal-to-noise ratio is disclosed. Specifically, the present disclosure relates to an elegant, novel circuit for measuring a plurality of biopotentials in useful in a variety of medical applications. This allows for robust, portable, low-power, higher S/N devices which have historically required a much bigger footprint.

A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.

A signal detection circuit includes: a first capacitor having a first terminal connected with a first main terminal of a switching element; a second capacitor having a first terminal connected with a second main terminal of the switching element; and a detection circuit having a differential circuit configuration. The detection circuit receives, as input signals, a signal from a second terminal of the first capacitor and a signal from a second terminal of the second capacitor, detects detection target signals based on the input signals. The detection target signals include a signal of the first main terminal of the switching element and a signal of the second main terminal of the switching element.

A distributed active, power combining amplifier including at least one main amplifier having a first main portion and a second main portion, at least one peaking amplifier having a first peaking portion and a second peaking portion, and a transformer having a primary side and a secondary side, the primary side having at least a first primary segment, a second primary segment, a third primary segment and a fourth primary segment, wherein the first main portion is coupled to the first primary segment and the second primary segment, the first peaking portion is coupled to the first primary segment or the second primary segment, the second main portion is coupled to the third primary segment and the fourth primary segment, and the second peaking portion is coupled to the third primary segment or the fourth primary segment in a symmetric architecture.

Technologies are provided for adaptive control of bias settings in a digital microphone. In some embodiments, a device includes a first component that provides data indicative of a clock frequency of operation in a functional mode of a digital microphone. The clock frequency clocks one or more microphone components having switching activity. The device also can include a second component that determines, using the clock frequency, an amount of bias current to supply to at least a first microphone component of the one or more microphone components. The device can further include a memory device that retains control parameters that include at least one of a first subset of parameters defining a relationship between current and frequency and a second subset of parameters defining a quantization of the relationship. The quantization including multiple bias current levels for respective frequency intervals.

Embodiments relate to a circuit implementation for extending the bandwidth of an amplifier. The extended bandwidth amplifier includes an amplifier coupled between an input node and an output node of the extended bandwidth amplifier. The amplifier has an input capacitance and an output capacitance. The extended bandwidth amplifier additionally includes a first digitally-trimmable negative-capacitance capacitor coupled between the input node of the extended bandwidth amplifier and a power supply terminal. The digitally-trimmable negative-capacitance capacitor includes a first branch, a second branch, and a controller. The first branch includes a first capacitor having a first negative capacitance, and a first switch. The second branch includes a second capacitor having a second negative capacitance, and a second switch. The controller is configured to turn on the first switch and the second switch based on the input capacitance of the amplifier.