In accordance with embodiments of the present disclosure, a system may have a configurable control loop technology, wherein the system comprises a first mode control loop, a second mode control loop and a reconfigurable pulse width modulator (PWM) configured to generate an output signal from an input signal. The reconfigurable PWM may include a digital PWM and an analog PWM and may be configured such that when the first mode control loop is activated, the reconfigurable PWM utilizes the analog PWM to generate the output signal from the input signal and when the second mode control loop is activated, the reconfigurable PWM utilizes the digital PWM to generate the output signal from the input signal and the digital PWM receives its input from a digital proportional integral derivative controller.

Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, S.sub.IN, and a first clock signal f.sub.SW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.

An impedance measurement circuit for determining a sense current of a guard-sense capacitive sensor operated in loading mode. The circuit includes a periodic signal voltage source for providing a periodic measurement voltage, a sense current measurement circuit, a differential amplifier that is configured to sense a complex voltage difference between the sense electrode and the guard electrode, a demodulator for obtaining, with reference to the periodic measurement voltage, an in-phase component and a quadrature component of the sensed complex voltage difference, and control loops for receiving the in-phase component and the quadrature component, respectively. An output signal of the first control loop and an output signal of the second control loop are usable to form a complex voltage that serves as a complex reference voltage for the sense current measurement circuit.

Disclosed herein are implantable medical devices (IMDs) including a receiver and a battery, and methods for use therewith. The receiver includes first and second differential amplifiers, each of which monitors for a predetermined signal within a frequency range and drains power from the battery while enabled, and while not enabled drains substantially no power from the battery. To remove undesirable input offset voltages, each of the differential amplifiers, while enabled, is selectively put into an offset correction phase during which time the predetermined signal is not detectable by the differential amplifier. At any given time at least one of the first and second differential amplifiers is enabled without being in the offset correction phase so that at least one of the differential amplifiers is always monitoring for the predetermined signal. In this manner, the receiver is never blind to signals, including the predetermined signals, sent by another IMD.

Disclosed herein are implantable medical devices (IMDs) including a receiver and a battery, and methods for use therewith. The receiver includes first and second differential amplifiers, each of which monitors for a predetermined signal within a frequency range and drains power from the battery while enabled, and while not enabled drains substantially no power from the battery. To remove undesirable input offset voltages, each of the differential amplifiers, while enabled, is selectively put into an offset correction phase during which time the predetermined signal is not detectable by the differential amplifier. At any given time at least one of the first and second differential amplifiers is enabled without being in the offset correction phase so that at least one of the differential amplifiers is always monitoring for the predetermined signal. In this manner, the receiver is never blind to signals, including the predetermined signals, sent by another IMD.

A multi-phase amplifier circuit includes an amplification circuit configured to generate a plurality of phase signals and to provide the plurality of phase signals to a plurality of inductors. An inductive coupling between a first pair of inductors differs from an inductive coupling between a second pair of inductors by a first coupling difference. The amplification circuit is configured to provide two phase signals comprising a first phase difference of less than 180 to the first pair of inductors and two further phase signals comprising the first phase difference to the second pair of inductors. An inductive coupling between a third pair of inductors differs from an inductive coupling between a fourth pair of inductors by a second coupling difference. The amplification circuit is configured to provide two phase signals comprising a second phase difference of 180 to the third pair of inductors and two further phase signals comprising the second phase difference to the fourth pair of inductors.

A BGR circuit for sub-1V ICs utilizes a voltage chopping circuit and/or a current chopping circuit and a low-frequency filter to stabilize the output reference voltage that is generated by an op-amp, a current mirror circuit, a CTAT stage, a PTAT stage, and an output stage. The voltage chopping circuit reduces input offset and 1/f noise by periodically alternating (time-averaging) the negative temperature dependent and positive temperature dependent voltages supplied by the CTAT and PTAT stages to the op-amp's input terminals. The current chopping circuit minimizes current variations caused by process-related differences in the current mirror devices by periodically alternating (time-averaging) three balanced currents generated by the current mirror circuit such that each current is transmitted equally to each of the CTAT, PTAT and output stages. The filter serves to maintain loop stability and remove the low frequency noise generated by the applied voltage and/or current chopping operations.

A BGR circuit for sub-1V ICs utilizes a voltage chopping circuit and/or a current chopping circuit and a low-frequency filter to stabilize the output reference voltage that is generated by an op-amp, a current mirror circuit, a CTAT stage, a PTAT stage, and an output stage. The voltage chopping circuit reduces input offset and 1/f noise by periodically alternating (time-averaging) the negative temperature dependent and positive temperature dependent voltages supplied by the CTAT and PTAT stages to the op-amp's input terminals. The current chopping circuit minimizes current variations caused by process-related differences in the current mirror devices by periodically alternating (time-averaging) three balanced currents generated by the current mirror circuit such that each current is transmitted equally to each of the CTAT, PTAT and output stages. The filter serves to maintain loop stability and remove the low frequency noise generated by the applied voltage and/or current chopping operations.

Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled to the output of the amplifier and using a first periodic reference signal waveform; and a second PWM having an input coupled to the output of the amplifier and using a second periodic reference signal waveform, wherein the second periodic reference signal waveform is 180 degrees out of phase from the first periodic reference signal waveform. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; and a plurality of pulse width modulators (PWMs) each having an input coupled to the output of the amplifier and using a corresponding unique one of a plurality of periodic reference signal waveforms, wherein the plurality of periodic reference signal waveforms are shifted in phase.

An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.