An output gain of a latch circuit is increased. The latch circuit includes a first circuit, a second circuit, and first to fourth transistors. The latch circuit includes a first input/output terminal and a second input/output terminal. The first circuit and the second circuit have a function of a current source. In the case where the third transistor is off and the fourth transistor is on, the latch circuit is supplied with a first input signal supplied to the first input/output terminal and a second input signal supplied to the second input/output terminal. In the case where the third transistor is on and the fourth transistor is off, an inverted signal of the first input signal is output to the first input/output terminal of the latch circuit, and an inverted signal of the second input signal is output to the second input/output terminal of the latch circuit. The first circuit and the second circuit increase the output gain of the latch circuit.

An automatic gain control system for a receiver, including: an automatic gain control loop (40) adapted to be coupled to both a first transimpedance amplifier (12) coupled to a first analog-to-digital converter (14) forming a first tributary and a second transimpedance amplifier (12) coupled to a second analog-to-digital converter (14) forming a second tributary; and an offset gain control voltage to gain balance a transimpedance amplifier gain of the first tributary and a transimpedance amplifier gain of the second tributary. The automatic gain control loop can be analog. Also, the automatic gain control loop can be implemented in hardware or firmware.

A variable gain amplifier includes a first transconductor circuit coupled to a first input terminal, a first output terminal, and a second output terminal of the variable gain amplifier, the first transconductor circuit including: a plurality of positive coefficient transistors coupled to the first output terminal and configured to selectively conduct current in response to a first binary code, a plurality of negative coefficient transistors coupled to the second output terminal and configured to selectively conduct current in response to a second binary code, and a plurality of amplifying transistors, each having a gate electrode coupled to the first input terminal, a first electrode coupled to a ground reference, and a second electrode coupled to a pair of coefficient transistors including one of the plurality of positive coefficient transistors and one of the plurality of negative coefficient transistors.

An application specific integrated circuit (ASIC) can drive semiconductor devices, such as, radio frequency amplifiers, switches, etc. The ASIC can include a supply and reference voltage generation circuit, a digital core, a clock generator, a plurality of analog-to-digital converters, low and high-speed communications interfaces, drain and gate sensing circuits (that can include one or more current sense amplifiers), and a gate driver circuit. The ASIC can be a low voltage semiconductor integrated circuit.

Techniques for controlling a low-dropout (LDO) voltage regulator. In an example, an LDO voltage regulator circuit includes an amplifier having an output coupled to a transistor. First and second inputs of the amplifier are coupled to a power supply node via first and second resistors, respectively. The transistor gate is coupled to the amplifier output, the transistor source is coupled to the second input of the amplifier, and the transistor drain is coupled to a reference voltage node. The second resistor is variable based on the amplifier output and a reference voltage from the reference voltage node. In an example, the reference voltage node is connectable to ground via a reference resistor connected in parallel with a noise-filtering capacitor, which causes a reference current to flow through the transistor. The reference current is adjusted based on the drain-to-source voltage of the transistor.

An amplifier includes a first differential input pair of transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. A second differential input pair of transistors has a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal. The first input terminal is coupled to the third input terminal, the second input terminal is coupled to the fourth input terminal, the first output terminal is coupled to the third output terminal, and the second output terminal is coupled to the fourth output terminal. A cross-over circuit has a control input coupled to the second fourth input terminals. The cross-over circuit is configured to vary an amount of bias current through the second differential input pair of transistors based on a magnitude of a voltage on the second and fourth input terminals.

An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port V.sub.in and an output port V.sub.out to form a differential input stage and N subsequent gain stages, a capacitive load C.sub.L coupled to the output port V.sub.out, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ω.sub.t of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ω.sub.t.

An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2π.Math.fc.Math.C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.

An apparatus for turning off a cascode amplifier having a common-base transistor and a common-emitter transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a collector-voltage from the collector of the common-emitter transistor when the common-emitter transistor is switched to a first OFF state and produce a first feedback signal. The collector-voltage is equal to an emitter voltage of the common-base transistor and the collector-voltage increases in response to switching the common-emitter transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first base-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first base-voltage and a second base-voltage. The common-base transistor is configured to switch to a second OFF state in response to receiving the second base-voltage.

A circuit is disclosed, in accordance with some embodiments. The circuit includes a transistor stage, a resistive element, a first tunable capacitive element and a second tunable capacitive element. The transistor stage includes a first input/output terminal and a second input/output terminal. The resistive element is connected to the transistor stage. The first tunable capacitive element is connected in parallel with the resistive element. The second tunable capacitive element is connected to the second input/output terminal of the transistor stage.