An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

A current mirror circuit that amplifies a reference current generated by a current source at a first magnification to supply a mirror current to a load circuit. The current mirror circuit includes a first transistor and a second transistor that share a power supply, and a drain potential mirror unit that amplifies the reference current at a second magnification to generate a first current, that amplifies a generated first current at a third magnification to generate a second current, and that supplies a predetermined potential determined based on the second current to a drain of the second transistor. The mirror current is supplied from the second transistor to the load circuit based on a potential of a gate of the first transistor determined based on the reference current.

Provided is a semiconductor integrated circuit including a pad Pd1 provided on one end side of a resistive element R1 externally provided, a pad Pd5 provided on a different end side of the resistive element R1; an operation amplifier A1, a signal line L11 wired between an output terminal of the operation amplifier A1 and the pad Pd1, a signal line L21 wired between an inverting input terminal of the operation amplifier A1 and the pad Pd5, a ESD protection element r11 provided to the signal line L11, and a signal line L31, through which a voltage signal of the pad Pd1 is transmitted. The signal line L31 is connected to the pad Pd1.

Provided is a semiconductor integrated circuit including a pad Pd1 provided on one end side of a resistive element R1 externally provided, a pad Pd5 provided on a different end side of the resistive element R1; an operation amplifier A1, a signal line L11 wired between an output terminal of the operation amplifier A1 and the pad Pd1, a signal line L21 wired between an inverting input terminal of the operation amplifier A1 and the pad Pd5, a ESD protection element r11 provided to the signal line L11, and a signal line L31, through which a voltage signal of the pad Pd1 is transmitted. The signal line L31 is connected to the pad Pd1.

A system includes a transimpedance amplifier, disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section. The arrangement provides low noise power supply for the front-end section, while providing a more power efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

A system includes a transimpedance amplifier, disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section. The arrangement provides low noise power supply for the front-end section, while providing a more power efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.

An ultrasound circuit comprising a multi-stage trans-impedance amplifier (TIA) is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA may include multiple stages, at least two of which operate with different supply voltages. The TIA may be followed by further processing circuitry configured to filter, amplify, and digitize the signal produced by the TIA.

An ultrasound circuit comprising a multi-stage trans-impedance amplifier (TIA) is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA may include multiple stages, at least two of which operate with different supply voltages. The TIA may be followed by further processing circuitry configured to filter, amplify, and digitize the signal produced by the TIA.

A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.