Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2.sup.N amplifiers where N is a positive integer. By the capacitive sensor chip based on the power-aware dynamic charge-domain amplifier array, utilization efficiency of charges can be effectively improved, power consumption overheads nay be effectively saved, energy efficiency of a system is greatly improved and a driving capability of the subsequent-stage amplifier may be adaptively distributed according to the size of an input capacitance.

Correlated double sampling column-level readout of an image sensor pixel may be provided by a charge transfer amplifier that is configured and operated to itself provide for both correlated-double-sampling and amplification of floating diffusion potentials read out from the pixel onto a column bus after reset of the floating diffusion (I) but before transferring photocharge to the floating diffusion (the reset potential) and (ii) after transferring photocharge to the floating diffusion (the transfer potential). A common capacitor of the charge transfer amplifier may sample both the reset potential and the transfer potential such that a change in potential (and corresponding charge change) on the capacitor represents the difference between the transfer potential and reset potential, and the magnitude of this change is amplified by the charge change being transferred between the common capacitor and a second capacitor selectively coupled to the common capacitor.

In described examples, a charge sensitive amplifier (CSA) generates an integrated signal in response to a current signal. A high pass filter is coupled to the CSA and receives the integrated signal and an inverse of an event signal, the high pass filter generates a coarse signal. An active comparator is coupled to the high pass filter and receives the coarse signal and a primary reference voltage signal, the active comparator generates the event signal.

In described examples, a charge sensitive amplifier (CSA) generates an integrated signal in response to a current signal. A high pass filter is coupled to the CSA and receives the integrated signal and an inverse of an event signal, the high pass filter generates a coarse signal. An active comparator is coupled to the high pass filter and receives the coarse signal and a primary reference voltage signal, the active comparator generates the event signal.

A read-out circuit includes an operational amplifier configured to receive input voltage via a positive input terminal; a feedback capacitor connected between an output terminal of the operational amplifier and a negative input terminal of the operational amplifier; a sensor charging/discharging circuit configured to charge or to discharge a sensor capacitor included in a sensor during a first time; and a switching circuit configured to connect the sensor capacitor and the operational amplifier during a second time after the sensor capacitor is charged or discharged.

In accordance with an example embodiment, a preamplifier circuit is provided, the preamplifier circuit comprising an amplifier arranged in a first current path between an input node and an output node of the preamplifier circuit; a feedback capacitor arranged in a second current path between said input node and said output node; a feedback circuit having an adjustable transfer function arranged in a third current path between said input node and said output node; a reset switch arranged in said third current path to enable selectively coupling the output of the feedback circuit to the input of the amplifier and decoupling the output of the feedback circuit from the input of the amplifier; and a loop controller arranged to selectively, in dependence of a voltage in the preamplifier circuit, one of open the reset switch to set the preamplifier circuit in a normal operating mode and close the reset switch to set the preamplifier circuit in a reset mode, wherein the loop controller is arranged to adjust the transfer function of the feedback circuit at least in part in dependence of the current operating mode of the preamplifier circuit.

In accordance with an example embodiment, a preamplifier circuit is provided, the preamplifier circuit comprising an amplifier arranged in a first current path between an input node and an output node of the preamplifier circuit; a feedback capacitor arranged in a second current path between said input node and said output node; a feedback circuit having an adjustable transfer function arranged in a third current path between said input node and said output node; a reset switch arranged in said third current path to enable selectively coupling the output of the feedback circuit to the input of the amplifier and decoupling the output of the feedback circuit from the input of the amplifier; and a loop controller arranged to selectively, in dependence of a voltage in the preamplifier circuit, one of open the reset switch to set the preamplifier circuit in a normal operating mode and close the reset switch to set the preamplifier circuit in a reset mode, wherein the loop controller is arranged to adjust the transfer function of the feedback circuit at least in part in dependence of the current operating mode of the preamplifier circuit.

A dynamic amplifier includes a common-source amplifier configured to receive a gate voltage at a gate node and output a drain current to a drain node; a current mirror configured to mirror the drain current into an output current to an output current; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage; a second switch configured to conditionally connect the gate node to a gate-resetting voltage; a third switch configured to conditionally connect the source node to a source-resetting voltage; a fourth switch configured to conditionally connect the drain node to a drain-resetting voltage; and a fifth switch configured to conditionally connect the output node to an output-resetting voltage.

It is described a charge preamplifier device (100) integrated in a chip (200) of semiconductive material comprising: an input (IN) for an input signal (i.sub.IN) and an output (OUT) for an output signal (v.sub.OUT); a substrate (202) of semiconductive material doped according to a first type of conductivity; an electrically insulating layer (204) placed on said substrate (202); a feedback capacitor (C.sub.f) integrated in the chip (200) and comprising a first electrode (3) connected to the input (IN) and a second electrode (2) connected to the output (OUT). The second electrode (2) is formed by a doped conductive region (205) having a second type of conductivity, opposite to the first type of conductivity, and integrated in the substrate (202) in order to face the first electrode (3).

It is described a charge preamplifier device (100) integrated in a chip (200) of semiconductive material comprising: an input (IN) for an input signal (i.sub.IN) and an output (OUT) for an output signal (v.sub.OUT); a substrate (202) of semiconductive material doped according to a first type of conductivity; an electrically insulating layer (204) placed on said substrate (202); a feedback capacitor (C.sub.f) integrated in the chip (200) and comprising a first electrode (3) connected to the input (IN) and a second electrode (2) connected to the output (OUT). The second electrode (2) is formed by a doped conductive region (205) having a second type of conductivity, opposite to the first type of conductivity, and integrated in the substrate (202) in order to face the first electrode (3).