In a first balun of a radio-frequency circuit, a first end of a first coil is connected to an amplifier, and a second end of the first coil is connected to a ground. In the first balun, a first end of a second coil is connected to a first switch, and a second end of the second coil is connected to a second switch. In a second balun, a first end of a third coil is connected to the first end of the second coil via the first switch, and a second end of the third coil is connected to the second end of the second coil via the second switch. In the second balun, a first end of a fourth coil is connected to a filter, and a second end of the fourth coil is connected to the ground.

A high-efficiency high-integrated receiver is provided. The radar receiver according to an embodiment of the present disclosure includes a receiver configured to receive a radar signal, a processor configured to attenuate a magnitude of a low frequency band of the received signal of the receiver, a filter configured to perform a low pass filtering on an output signal of the processor, and an ADC configured to A/D convert the output signal of the filter. Accordingly, it is possible to demodulate all the signals being reflected from targets in various distances when even using a low resolution ADC, thereby reducing the manufacturing cost and power consumption.

Amplifier systems and methods are provided that include a fixed gain amplification stage coupled to an adjustable attenuation stage further coupled to a variable gain amplification stage. A controller controls an amount of attenuation provided by the adjustable attenuation stage and an amount of gain provided by the variable gain amplification stage to maintain any of various noise, efficiency, and/or linearity requirements of the amplifier system.

A main line (transmission line) has a first end and a second end. A sub-line (transmission line) coupled to the main line has a third end and a fourth end. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. An unbalanced node is connected to the first end. The first balanced node is connected to the first end, and the second balanced node is connected to the fourth end. The second end and the third end are connected to a reference potential. A first LC resonant circuit is connected between the first balanced node and the unbalanced node, the second balanced node and the fourth end, or the first end and the unbalanced node.

A main line (transmission line) having a first end and a second end. A sub-line (transmission line) coupled to the main line. An unbalanced signal is input to and output from an unbalanced node connected to the first end. A balanced signal is input to and output from a first balanced node and a second balanced node. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. The second end and the third end are connected to a reference potential. The first balanced node and the second balanced node are connected to the unbalanced node and the fourth end, respectively. A first LC resonant circuit is connected between the second end and the reference potential or the third end and the reference potential.

An active balun amplifier includes a first plurality of metal oxide semiconductor (MOS) transistors arranged in series, the first plurality of MOS transistors comprising a first input transistor of a first conductivity type, a second input transistor of a second conductivity type, and at least two common-gate transistors arranged in series between the first input transistor and the second input transistor, wherein a gate of the first input transistor and a gate of the second input transistor are tied to a common input, a second plurality of MOS transistors arranged in series, the second plurality of MOS transistors comprising a first common-source transistor of the first conductivity type, a second common-source transistor of the second conductivity type, and at least two cascode transistors arranged in series between the first common-source transistor and the second common-source transistor.

A stacked amplifier circuit includes an input stage having first and second input ports respectively defined by inputs of first and second transistors. A transformer arrangement includes first and second primary windings and first and second secondary windings. The first secondary winding is connected to an output of the first input transistor and the second secondary winding is connected to an output of the second input transistor. Portions of the magnetic fields generated by the primary windings couple to their respective secondary windings. An output stage is AC coupled to the first and second secondary windings and has an output connected to the first and second primary windings. The input stage and the output stage are arranged in a stacked configuration such that a bias current of the output stage is reused as bias current for the input stage.

There is provided a RF-DAC that may include (i) a first PAM that includes a first group of first power amplifiers of different amplifications, (ii) a second PAM that includes a second group of second power amplifiers of different amplifications; (iii) a load that includes an output port and a transformer; (iv) power amplifiers control units, and a transformer control unit. During a cycle of operation (i) each one of the first and second PAMs is configured to receive one or more power amplifiers digital control signals and activate a single power amplifier per each of the first and second PAMS, (ii) the transformer control unit is configured to receive a transformer digital control signal and control a transformer parameter of the transformer, and (iii) the transformer is configured to receive a first PAM output signal and a second PAM output signal, and output a transformer output signal that reflects digital information represented by the one or more power amplifiers digital control signals and the transformer digital control signal.

An apparatus includes a phased array antenna panel and one or more beam former circuits mounted on the phased antenna array panel. The phased array antenna panel generally comprises a plurality of antenna elements arranged in one or more groups. Each of the one or more beam former circuits may be coupled to a respective group of the antenna elements. Each of the one or more beam former circuits may comprise a plurality of transceiver channels. Each transceiver channel generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive a respective one of the antenna elements. The power amplifier generally comprises a feedback network coupled between an output and an input of the power amplifier circuit.

A power amplifier (20) for a transmitter circuit (10) is disclosed. The power amplifier (20) comprises at least one field-effect transistor (100, 100n, 100p) having a gate terminal (110, 110n, 110p) and a bulk terminal (120, 120n, 120p), wherein the at least one field-effect transistor (100, 100n, 100n) is configured to receive an input voltage at the gate terminal (110, 110p, 110n) and a dynamic bias voltage at the bulk terminal (120, 120n, 120p). Furthermore, the power amplifier (20) comprises a bias-voltage generation circuit (130). The input voltage is a linear function of an input signal. The bias-voltage generation circuit (130) is configured to generate the dynamic bias voltage as a nonlinear function of an envelope of the input signal.