A wireless communication device configured to prevent a transmission time period for sending a wireless signal and a receiving time period for receiving a wireless signal from being overlap, comprises: a transmitter that includes an orthogonal modulator that orthogonally modulates an IQ-modulated modulation signal and a transmission power amplifier that power-amplifies the orthogonally modulated signal; a receiver that includes a demodulator that demodulates a received signal; a first power source that is the power source for the transmission power amplifier and the receiver; and a second power source that is the power source for the orthogonal modulator; and a controller which outputs the modulation signal to the orthogonal modulator. The first power source outputs a constant voltage to the receiver during the receiving time period, and outputs, during the transmission time period, to the transmission power amplifier, a fluctuating voltage according to an envelope of the modulation signal.

An envelope tracking arrangement is disclosed and includes a level select component, a chunk supply component and a power amplifier. The level select component is configured to segment an input signal into chunks based on time and to select a chunk level for each chunk based on information or envelope information. The chunk supply component is configured to selectively provide a discrete supply voltage according to the selected chunk level. The power amplifier is configured to generate a radio frequency (RF) output signal based on the input signal and utilizing the discrete supply voltage.

A supply modulator for providing a first power supply voltage and a second power supply voltage to a first power amplifier and a second power amplifier, respectively, includes a first modulation circuit including a linear regulator and a switching regulator, the first modulation circuit being configured to generate a first modulation voltage in accordance with envelope tracking, and provide the first modulation voltage to the first power amplifier as the first power supply voltage; and a single inductor multiple output converter configured to generate a first output voltage and a second output voltage based on an input voltage having a fixed level, provide the first output voltage to the linear regulator of the first modulation circuit as a power supply voltage, and provide the second output voltage to the second power amplifier as the second power supply voltage.

Disclosed herein are front-end modules that support carrier aggregation. Wireless communication configurations are disclosed that include a plurality of such front-end modules to support uplink and/or downlink carrier aggregation. Individual front end modules include a power amplifier module to amplify signals received at a transceiver port and an envelope tracker to increase efficiency of the power amplifier module. The front-end modules include a multiplexer and an antenna switch module with a plurality of duplexers between them along a corresponding plurality of paths. One path includes a first duplexer configured to process frequency division duplex (FDD) signals and another path includes a second duplexer configured to process time division duplex (TDD) signals. The front-end modules also include a low noise amplifier module coupled to the second duplexer to amplify TDD signals while received FDD signals are directed off module for amplification.

A power supply circuit includes a plurality of power amplifiers for amplifying radio frequency signals, an envelope tracker for supplying a variable voltage based on an envelope signal to the power amplifiers, a common line connected to an output side of the envelope tracker, and a plurality of branch lines branching from a tip of the common line and connected to the power amplifiers, respectively. On the branch lines, sub-inductors are provided, respectively. On the common line, a main inductor and a capacitor are provided.

Provided is a receiver including an oscillator (OSC) configured to generate an oscillation signal based on a radio signal, a clocked envelope detector (ED) configured to detect an envelope of the oscillation signal and hold a peak value of the envelope during a time interval, and an analog-to-digital converter (ADC) configured to convert the peak value of the envelope into a digital signal.

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

A power amplifier power supply circuit includes a first power supply circuit and a second power supply circuit that are connected in parallel, where the first power supply circuit and the second power supply circuit jointly supply power to a power amplifier by using a power supply end of the power amplifier. The second power supply circuit is configured to adjust a power supply voltage of the power amplifier at a symbol level. Power supply voltages output by the second power supply circuit and the first power supply circuit change based on a change of an envelope signal output by the power amplifier.

A distributed power management apparatus is provided. The distributed power management apparatus includes an envelope tracking (ET) integrated circuit (ETIC) and a distributed ETIC separated from the ETIC. The ETIC is configured to generate a number of ET voltages for a number of power amplifier circuits and the distributed ETIC is configured to generate a distributed ET voltage(s) for a distributed power amplifier circuit(s). In a non-limiting example, the number of power amplifier circuits and the distributed power amplifier circuit(s) can be disposed on opposite sides (e.g., top and bottom) of a wireless device. As such, in embodiments disclosed herein, the ETIC is provided closer to the power amplifier circuits and the distributed ETIC is provided closer to the distributed power amplifier circuit(s). By providing the ETIC and the distributed ETIC closer to the respective power amplifier circuits, it is possible to reduce trace inductance and unwanted signal distortion.

An equalizer circuit and related power management circuit are provided. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit(s) via a signal path for amplifying a radio frequency signal(s). An equalizer circuit is provided in the power management circuit to equalize the differential target voltage prior to generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function including a second-order complex-zero term and a real-zero term for offsetting a transfer function of an inherent trace inductance of the signal path and an inherent impedance of the voltage amplifier circuit. By employing the second-order transfer function with the real-zero term, it is possible to reduce distortion in the ET voltage, especially when the RF signal(s) is modulated in a wide modulation bandwidth.