A power supply circuit and an apparatus includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, and a second capacitor. In this power supply circuit, one terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the first capacitor is separately connected to a first electrode of the first switching transistor and a first electrode of the second switching transistor, a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor, a second electrode of the second switching transistor is connected to a second electrode of the fourth switching transistor, a third electrode of the first switching transistor is connected to an output node, and a third electrode of the second switching transistor is grounded.

An apparatus of a transmitter and method are provided, the apparatus comprising a processor that calculates a supply voltage (SV) value (SVV) to provide as an SV for a power amplifier (PA) of the transmitter for transmissions during a transmission time slot (TS). When the SV<an envelope tracking (ET) threshold (ETT), then the processor configures the PA to transmit a signal in an average power tracking (APT) mode that maintains the SV at the SVV during the TS. When the SVETT, and an APT condition is met, then the processor configures the PA to transmit the signal in the APT mode. When the SVETT, and the APT condition is not met, then the processor transmits by an adjustment to the SVV to track an amplitude modulation envelope during the TS in an ET mode.

An envelope tracking (ET) amplifier circuit is provided. The ET amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulated voltage. The ET modulated voltage corresponds to a time-variant voltage envelope, which can be misaligned from a time-variant signal envelope of the RF signal due to inherent temporal delay in the ET amplifier circuit. As a result, the amplifier circuit may suffer degraded linearity performance. In this regard, a voltage processing circuit is provided in the ET amplifier circuit and configured to operate in a low-bandwidth mode and a high-bandwidth mode. In the high-bandwidth mode, the voltage processing circuit is configured to cause the ET modulated voltage to be modified to help improve delay tolerance of the ET amplifier circuit. As a result, it may be possible to reduce linearity degradation of the amplifier circuit to a predetermined threshold.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

A power amplification circuit includes an amplification transistor, a variable voltage power supply that supplies a variable voltage to a collector of the amplification transistor, a bias circuit that has a constant current amplification transistor outputting a DC bias current to a base of the amplifier transistor, and a current limiting circuit that limits the DC bias current. The current limiting circuit includes a current limiting transistor, a resistor element connected to a collector of the current limiting transistor and the variable voltage power supply, and a resistor element connected to a base of the current limiting transistor and a base of the constant current amplifying transistor.

Power amplifier (PA) output memory neutralization is disclosed, using baseband input/output (I/O) capacitance current compensation. Radio frequency (RF) PAs experience I/O memory effects when used with envelope tracking supply modulation schemes. Envelope tracking supply modulation results in a nonlinear variation of the I/O capacitance. Traditional approaches compensate for such effects with a current provided by a bias circuit which is band-limited. This results in memory effects which distort the amplified signal, becoming more significant as the modulation bandwidth increases. An RF communications system according to embodiments disclosed herein mitigates such memory effects by compensating for the non-linear effect of the I/O capacitance in an RF PA.

Disclosed are systems, devices, modules, methods, and other implementations, including a method for digital predistortion that includes receiving, by a digital predistorter, a first signal that depends on amplitude variations based on an input signal, u, with the variations of the first signal corresponding to time variations in non-linear characteristics of a transmit chain that includes a power amplifier. The method further includes receiving, by the digital predistorter, the input signal u, generating, by the digital predistorter, based at least in part on signals comprising the input signal u and the first signal, a digitally predistorted signal v to mitigate the non-linear behavior of the transmit chain, and providing the predistorted signal v to the transmit chain.

An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce footprint and improve heat dissipation of the ET power amplifier apparatus.

An envelope tracking system having delay compensation circuitry is disclosed. The envelope tracking system includes transmit circuitry configured to receive an input transmit signal, a gain control signal, and delay compensation values. The envelope tracking system is further configured to generate an envelope tracking signal based on the input transmit signal, the gain control signal, and the delay compensation values, and generate an output transmit signal based on the input transmit signal. The envelope tracking system also includes a power amplifier configured to generate an amplified transmit signal based on the output transmit signal and an operating voltage. The envelope tracking system further includes an envelope tracking integrated circuit configured to control the operating voltage based on the envelope tracking signal. The delay compensation circuitry is configured to generate the delay compensation values based on a peak-to-average ratio of a given modulation type and the gain control signal.