Patent classifications
H03F2200/105
Power supply for radio-frequency power amplifier
A power supply for a radio-frequency power amplifier includes: first and second linear circuits, configured to linearly amplify a low-power signal and a high-power signal in a first envelope signal respectively and provide first and second voltages to the radio-frequency power amplifier respectively, wherein the low-power signal is a signal with a power ratio less than or equal to 30% in the envelope signal, and the high-power signal other than the low-power signal is a signal with a power ratio greater than or equal to 70% in the envelope signal; and a third circuit, configured to detect the linearly-amplified high-power signal and work in a constant on time control mode having a constant on time or a constant off time control mode having a constant off time so as to provide a third electric current to the radio-frequency power amplifier according to the detected linearly-amplified high-power signal.
Power amplifiers with adaptive bias for envelope tracking applications
Power amplifiers with adaptive bias for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The power amplifier includes a field-effect transistor (FET) for amplifying the RF signal, and a current mirror including an input that receives a reference current and an output connected to the power amplifier supply voltage. An internal voltage of the current mirror is used to bias the gate of the FET to compensate the FET for changes in the power amplifier supply voltage arising from envelope tracking.
ELECTRONIC DEVICE INCLUDING POWER MANAGEMENT INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF
An electronic device includes a battery, a plurality of capacitors, a converter that receives power from the battery and charges each of the plurality of capacitors to different voltages based on the power, a plurality of switches that switch a first path and a second path of each of the plurality of capacitors, and a controller. The controller selects a first switch among the plurality of switches based on a received signal, and controls the first switch such that a path of a capacitor connected to the first switch is switched from the first path to the second path, and the first path is a path which electrically connects each of the plurality of capacitors to the converter, the second path is a path which electrically connects each of the plurality of capacitors and a power amplifier (PA).
APPARATUS AND METHODS FOR DETECTING AND CLAMPING POWER OF A POWER AMPLIFIER
Apparatus and method for detecting and clamping power of a power amplifier are disclosed. In certain embodiments, a power amplifier system includes a power amplifier that amplifies a radio frequency input signal to generate a radio frequency output signal, a bias circuit that controls a bias of the power amplifier, a radio frequency coupler that generates a radio frequency coupled signal based on the radio frequency output signal, a clamp that selectively clamps the bias of the power amplifier, and a power detector that controls the clamp based on the radio frequency coupled signal.
ELECTRONIC DEVICE AND METHOD FOR CONTROLLING POWER SUPPLIED TO TRANSMIT SIGNAL
An electronic device includes an antenna, a communication circuit, and a processor. The communication circuit includes a first amplifier configured to amplify a radio frequency signal; a first coupler configured to output a first amplifier output signal output from the first amplifier, to the antenna through a first port, and output at least a part of the first amplifier output signal to a first switch through a second port; and a second amplifier configured to amplify the second portion of the first amplifier output signal, output from the first switch. The processor is operably connected to the antenna and the communication circuit, wherein the processor is configured to, based on a magnitude of the first amplifier output signal, control the first switch and the second switch to use the first amplifier, or to use the first amplifier and the second amplifier.
Wireless Communication Apparatus, System, and Signal Processing Method
This application discloses a wireless communication apparatus and a signal processing method. The wireless communication apparatus includes a power amplifier and a bias circuit. The power amplifier includes a signal input port, a signal output port, a power supply port, and a bias port. The power amplifier is configured to: receive a power supply signal through the power supply port, receive a bias signal through the bias port, receive a radio frequency signal through the signal input port, and output a power amplified radio frequency signal. The bias circuit is configured to generate the bias signal. A timing feature of the bias signal is synchronized with a timing feature of a switch signal of a power amplifier, to compensate for a nonlinear change in the TDD scenario.
Method and apparatus for supplying voltage to amplifier using multiple linear regulators
Various embodiments disclose a method and a device. The device includes: an antenna; a switching regulator; a communication chip including an amplifier, a first linear regulator operably connected to the amplifier and the switching regulator and configured to be supplied with a first voltage from the switching regulator, and a second linear regulator operably connected to the amplifier and the switching regulator and configured to be supplied with a second voltage higher than the first voltage from the switching regulator, the communication chip configured to transmit a radio-frequency signal outside of the electronic device through the antenna; and a control circuit. The control circuit is configured to produce an envelope of an input signal input to the amplifier in connection with the radio-frequency signal and to provide the produced envelope to at least one of the first linear regulator or the second linear regulator. The first linear regulator is configured to provide a third voltage corresponding to the envelope to the amplifier using the first voltage based on the envelope having a voltage in a first range. The second linear regulator is configured to provide a fourth voltage higher than the third voltage to the amplifier using the second voltage based on the voltage of the envelope being in a second range including values larger than values included in the first range.
Supply generator and associated control methods
Described are concepts, circuits, systems and techniques directed toward N-phase control techniques useful in the design and control of supply generators configured for use in a wide variety of power management applications including, but not limited to mobile applications.
ENVELOPE DETECTOR CIRCUIT, CORRESPONDING RECEIVER CIRCUIT AND GALVANIC ISOLATOR DEVICE
A rectifier stage includes a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load circuit coupled between the intermediate node and a supply voltage node. The differential input transistor pair receives a radio-frequency amplitude modulated signal. A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal is produced at the intermediate node. An amplifier stage coupled to the intermediate node produces an amplified rectified signal at an output node that is indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage includes a resistive element coupled between the intermediate node and the supply voltage node in parallel to the load circuit.
Cascode amplifier bias circuits
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.