Patent classifications
H03F2200/108
Body tie optimization for stacked transistor amplifier
A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
Apparatus and methods for wide local area network power amplifiers
Apparatus and methods for wireless local area network (WLAN) power amplifiers are provided. In certain configurations, a WLAN power amplifier system includes a WLAN power amplifier, an output impedance matching network, and an envelope tracker. The WLAN power amplifier includes an input that receives a WLAN signal having a fundamental frequency and an output that generates an amplified WLAN signal for transmission over an antenna. The output impedance matching network is electrically connected to the output of the WLAN power amplifier, and can provide a load line impedance between 10 and 35 at the fundamental frequency. The envelope tracker receives an envelope of the WLAN signal, and controls a voltage level of a power supply of the WLAN power amplifier based on the envelope signal.
Amplifiers Operating in Envelope Tracking Mode or Non-Envelope Tracking Mode
Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.
POWER AMPLIFICATION MODULE
A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
Amplifiers operating in envelope tracking mode or non-envelope tracking mode
Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.
Power amplification module
A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
Bias control for stacked transistor configuration
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.
Dual-band low noise amplifier
An apparatus includes amplification circuitry configured to amplify a radio frequency (RF) signal. The apparatus also includes differential inductors coupled to an output of the amplification circuitry. The differential inductors include a first inductor serially coupled to a second inductor, and the differential inductors are configured to filter the RF signal and to provide a differential output.
RF power transistors with video bandwidth circuits, and methods of manufacture thereof
Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor, an impedance matching circuit, and a video bandwidth circuit. The impedance matching circuit is coupled between the transistor and an RF I/O (e.g., an input or output lead). The video bandwidth circuit is coupled between a connection node of the impedance matching circuit and a ground reference node. The video bandwidth circuit includes a plurality of components, which includes an envelope inductor and an envelope capacitor coupled in series between the connection node and the ground reference node. The video bandwidth circuit further includes a first bypass capacitor coupled in parallel across one or more of the plurality of components of the video bandwidth circuit.
OFF-CHIP DISTRIBUTED DRAIN BIASING OF HIGH POWER DISTRIBUTED AMPLIFIER MONOLITHIC MICROWAVE INTEGRATED CIRCUIT (MMIC) CHIPS
Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.