The present disclosure in some embodiments relates to a method of calibrating a power amplifier performance and an apparatus therefor, which provide an optimal calibration of the output characteristics of a power amplifier to all possible combinations in the input signal source by enabling individualized calibrations for changes in the output characteristics at room temperature and changing temperatures, thereby improving the performance of the power amplifier.

The present disclosure in some embodiments relates to a method of calibrating a power amplifier performance and an apparatus therefor, which provide an optimal calibration of the output characteristics of a power amplifier to all possible combinations in the input signal source by enabling individualized calibrations for changes in the output characteristics at room temperature and changing temperatures, thereby improving the performance of the power amplifier.

The present technology relates to an amplifier, an audio signal output method, and an electronic device that can inhibit unintended sound output in a class D amplifier that changes a peak value of a PWM signal. The amplifier includes: a positive-side amplitude generating circuit configured to generate positive-side amplitude of an output PWM signal that is a PWM signal to be output outside an apparatus; a negative-side amplitude generating circuit configured to generate negative-side amplitude of the output PWM signal; and a feedback circuit configured to feed back a difference between the amplitude generated by the positive-side amplitude generating circuit and the amplitude generated by the negative-side amplitude generating circuit to the positive-side amplitude generating circuit and the negative-side amplitude generating circuit. The present technology is applicable, for example, to an amplifier or the like of an electronic device such as an audio player.

The present technology relates to an amplifier, an audio signal output method, and an electronic device that can inhibit unintended sound output in a class D amplifier that changes a peak value of a PWM signal. The amplifier includes: a positive-side amplitude generating circuit configured to generate positive-side amplitude of an output PWM signal that is a PWM signal to be output outside an apparatus; a negative-side amplitude generating circuit configured to generate negative-side amplitude of the output PWM signal; and a feedback circuit configured to feed back a difference between the amplitude generated by the positive-side amplitude generating circuit and the amplitude generated by the negative-side amplitude generating circuit to the positive-side amplitude generating circuit and the negative-side amplitude generating circuit. The present technology is applicable, for example, to an amplifier or the like of an electronic device such as an audio player.

A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the differential input voltage. A feedback loop provides feedback from an output of the differential input stage amplifier to input tail current of the differential input stage amplifier. The feedback loop enables class AB operation of the differential input stage amplifier. At least one gain reducer is operatively coupled to the feedback loop to reduce the gain of the feedback loop. The gain reducer has a resistance value that varies inversely proportional to loop current in the feedback loop to reduce the gain of the feedback loop as loop current increases.

Embodiments of the present disclosure provide a transmitter system including: a source follower (SF) sub-stage having a pair of transistors, one being coupled to a biasing voltage at a gate terminal thereof, and the other including a fully depleted semiconductor on insulator (FDSOI) transistor coupled to an input signal at a gate terminal thereof, and coupled to a calibration voltage at a back-gate terminal thereof. A mixer sub-stage includes a mixer input node coupled to the SF output node of the pair of transistors of the SF sub-stage, and the mixer input node is electrically coupled in parallel to two FDSOI mixer transistors, with the FDSOI mixer transistor being electrically coupled to a respective back-gate voltage. The FDSOI mixer transistors each include a gate terminal coupled to an input voltage, while a second source/drain terminal of the FDSOI mixer transistors are each electrically coupled to a mixer output node.

A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the differential input voltage. A feedback loop provides feedback from an output of the differential input stage amplifier to input tail current of the differential input stage amplifier. The feedback loop enables class AB operation of the differential input stage amplifier. At least one gain reducer is operatively coupled to the feedback loop to reduce the gain of the feedback loop. The gain reducer has a resistance value that varies inversely proportional to loop current in the feedback loop to reduce the gain of the feedback loop as loop current increases.

A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the differential input voltage. A feedback loop provides feedback from an output of the differential input stage amplifier to input tail current of the differential input stage amplifier. The feedback loop enables class AB operation of the differential input stage amplifier. At least one gain reducer is operatively coupled to the feedback loop to reduce the gain of the feedback loop. The gain reducer has a resistance value that varies inversely proportional to loop current in the feedback loop to reduce the gain of the feedback loop as loop current increases.