H03F2200/156

Inrush current limiter circuits having current regulating switches therein
10938435 · 2021-03-02 · ·

Base station antennas utilize RF transmitters and receivers, which operate with enhanced bias control to achieve very high speed switching during TDD operation. A radio frequency communication circuit for TDD includes a transmit/receive amplifier (e.g., MMIC) having first and second input terminals, which are responsive to a bias control voltage and radio frequency input signal. A bias control circuit is provided, which is electrically coupled to the first input terminal and a current receiving terminal of the transmit/receive amplifier. The bias control circuit includes a closed-loop feedback path between the current receiving terminal and the first input terminal, which is configured to regulate a magnitude of the bias control voltage with high precision to thereby achieve a substantially constant quiescent bias current at the current receiving terminal when the transmit/receive amplifier is enabled.

SHUNT RESISTOR AVERAGING TECHNIQUES
20210048453 · 2021-02-18 ·

Techniques for improving current sensing via a shunt resistance are provided. In an example, an apparatus for sensing current can include a substrate, and a plurality of metal layers stacked on the substrate and separated from the substrate and from each other by an insulation material. In certain examples, a first one or more metal layers can form a sense resistance configured to pass current between a source and a load, and a second one or more metal layers can form one or more gain resistances coupled to the sense resistance and configured to couple to a current sense amplifier. In some example, a metal layer can include portions of both the sense resistance and the gain resistance to compensate for environmental anomalies, material anomalies or manufacturing anomalies.

High voltage sensing circuit, display driver integrated circuit and display apparatus including the same

A high voltage sensing circuit included in a display driver integrated circuit includes a plurality of channels, a plurality of sampling capacitors, an amplifier and a feedback capacitor. The plurality of channels receives a plurality of input voltages. The plurality of sampling capacitors are connected to the plurality of channels, respectively, to simultaneously sample the plurality of input voltages. The amplifier is configured to sequentially receive each of a plurality of sampled input voltages to sequentially generate a respective plurality of sensing voltages. The feedback capacitor is connected between an input terminal and an output terminal of the amplifier, and is shared by the plurality of channels. The amplifier and the feedback capacitor are configured such that each of the plurality of sampled input voltages is sequentially scaled to the respective one of the plurality of sensing voltages by the amplifier and the feedback capacitor.

Impedance measuring semiconductor circuit
10921359 · 2021-02-16 · ·

A provided impedance measuring semiconductor circuit can suppress the influence of sensors on the measurements of other sensors in the measurements of the sensors. According to an embodiment, an impedance measuring semiconductor circuit includes a first resistance element, an operational amplifier having a positive input terminal and an output terminal, the positive input terminal receiving a predetermined set voltage, the output terminal being coupled to one end of the first resistance element, a first output-side switch that electrically couples or decouples a first sensor and the other end of the first resistance element, a second output-side switch that electrically couples or decouples a second sensor and the other end of the first resistance element, a first input-side switch that electrically couples or decouples the first sensor and a negative input terminal, and a second input-side switch that electrically couples or decouples the second sensor and the negative input terminal.

Method of forming a semiconductor device and structure therefor

In an embodiment, a differential buffer may include a first input stage that compares a non-inverting portion of an input signal alternately to a non-inverting portion of an output and to an inverting portion of the output. Another embodiment of the differential buffer may also include a second input stage that compares the inverting portion of the input signal alternately to the inverting portion of the output signal and to the non-inverting portion of the output signal. Other embodiments of the differential buffer may include a feedback chopper switch that transfers the non-inverting portion of the output signal and the inverting portion of the output signal to the first input stage and to the second input stage.

5G NR configurable wideband RF front-end LNA

Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.

AMPLIFIER WITH ADAPTIVELY-CONTROLLED LOCAL FEEDBACK LOOP

In a general aspect, a circuit can include an input circuit configured to receive an input signal, and an amplifier circuit coupled with the input circuit. The amplifier circuit can include an amplifier, and first and second feedback paths. The first feedback path can be from a positive output to a negative input of the amplifier, and the second feedback path can be from a negative output to a positive input of the first amplifier. The circuit can also include a loop circuit configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and current flow into the negative input of the first amplifier. The circuit can also include a control circuit that is configured to enable the loop circuit in response to a magnitude of the input signal exceeding a threshold.

Amplifier configurable into multiple modes

This disclosure describes techniques for selecting one of a plurality of modes in which to operate an amplifier. The techniques include configuring input routing circuitry, coupled to first and second inputs of the amplifier, based on the selected one of the plurality of modes; selectively applying a resistance to an output of the amplifier, using feedback routing circuitry, based on the selected one of the plurality of modes; and selectively applying one of a plurality of reference voltages, using reference voltage routing circuitry, coupled to the first and the second inputs of the amplifier, based on the selected one of the plurality of modes.

METHOD AND SYSTEM FOR PROCESS AND TEMPERATURE COMPENSATION IN A TRANSIMPEDANCE AMPLIFIER USING A DUAL REPLICA
20210028748 · 2021-01-28 ·

The present disclosure provides for process and temperature compensation in a transimpedance amplifier (TIA) using a dual replica via monitoring an output of a first TIA (transimpedance amplifier) and a second TIA; configuring a first gain level of the first TIA based on a feedback resistance and a reference current applied at an input to the first TIA; configuring a second gain level of the second TIA and a third TIA based on a control voltage; and amplifying a received electrical current to generate an output voltage using the third TIA according to the second gain level. In some embodiments, one or both of the second TIA and the third TIA include a configurable feedback impedance used in compensating for changes in the second gain level due to a temperature of the respective second or third TIA via the configurable feedback impedance of the respective second or third TIA.

Current-mode circuits and calibration thereof
11863169 · 2024-01-02 · ·

A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.