A novel semiconductor device with high convenience or high reliability is provided. The semiconductor device includes an arithmetic logic unit and an amplifier. The arithmetic logic unit is configured to generate second data on the basis of an offset adjustment signal or offset data and first data. The amplifier includes an operational amplifier and an offset adjustment circuit including a register. The operational amplifier supplies a predetermined voltage to a node on the basis of a voltage between a first terminal and a second terminal. The register is configured to retain, as the offset data, the offset adjustment signal on the basis of a latch signal. The register is configured to allow the supplied offset adjustment signal to pass therethrough in a passage state and supply the offset adjustment signal. The register is configured to supply the offset data in a non-passage state.

An inductor includes a substrate, and a first coil pattern disposed on one surface of the substrate and having a spiral shape comprising a plurality of turns, wherein as the first coil pattern extends inwardly towards a center of the first coil pattern, a pattern width of the first coil pattern decreases while a center-to-center distance between two adjacent turns of the first coil pattern increases.

This disclosure describes techniques for selecting one of a plurality of modes in which to operate an amplifier. The techniques include configuring input routing circuitry, coupled to first and second inputs of the amplifier, based on the selected one of the plurality of modes; selectively applying a resistance to an output of the amplifier, using feedback routing circuitry, based on the selected one of the plurality of modes; and selectively applying one of a plurality of reference voltages, using reference voltage routing circuitry, coupled to the first and the second inputs of the amplifier, based on the selected one of the plurality of modes.

The present disclosure relates to a semiconductor device and a cell potential measuring apparatus capable of amplifying and reading a potential of solution with high accuracy. A reading electrode reads the potential of the solution. A differential amplifier includes a current mirror circuit. The reading electrode is connected to a first input terminal of the differential amplifier which is connected to a gate of a first input transistor connected to a diode-connected pMOS transistor of the current mirror circuit. An output terminal of the differential amplifier is connected to a second input terminal of the differential amplifier, which is connected to a gate of a second input transistor connected to a pMOS transistor of the current mirror circuit which is not diode-connected, via a capacitor. For example, the present disclosure is applied to the cell potential measuring apparatus and the like.

Methods and systems for process and temperature compensation in a transimpedance amplifier using a dual replica and configurable impedances is disclosed and may include a transimpedance amplifier (TIA) circuit comprising a first TIA, a second TIA, a third TIA, and a control loop. The first TIA comprises a fixed feedback resistance and the second and third TIAs each comprise a configurable feedback impedance. The system may comprise a gain stage with inputs coupled to outputs of the first and second TIAs and with an output coupled to the configurable feedback impedance of the second and third TIAs. The circuit may be operable to configure a gain level of the first TIA based on the fixed feedback resistance and a reference current applied at an input to the first TIA, and configure a gain level of the second and third TIAs based on a control voltage generated by the gain stage.

A reference voltage generator comprises: an amplifier; a capacitor network including one or more capacitors; and a switch control circuit to control connectivity of the capacitor network with respect to the input/output nodes of the amplifier. During operation, the switch control circuit controls connectivity of a first capacitor (in the capacitor network) in and out of a feedback path of the amplifier to produce a substantially constant reference voltage. For example, the reference voltage generator provides input offset voltage correction of the amplifier via repeatedly switching between: i) a first mode in which the first capacitor is absent from the feedback path of the amplifier during charging of the first capacitor, and ii) a second mode of inserting the charged first capacitor into the feedback path of the amplifier. Correction of the input offset voltage of the amplifier results in generation of a more accurate reference voltage over temperature.

A multi-stage amplifier with a high signal-to-noise ratio is introduced. Multiple amplification stages are cascaded between an input terminal and an output terminal of the amplifier. A controller switches the output stage among the multiple amplification stages from a normal mode to an attenuation mode in response to the amplifier input being lower than the threshold. In the attenuation mode, the output stage provides an attenuation resistor coupled in series with the load resistor of the amplifier. Noise is successfully attenuated by the attenuation-mode output stage.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

An apparatus includes an amplifying circuit configured to include stacked first and second transistors, and to amplify a signal input from an input terminal during an operation in an amplifying mode, and provide the amplified signal to an output terminal, and a negative feedback circuit comprising first to nth sub-negative feedback circuits, each corresponding to a separate gain mode included in the amplifying mode, wherein the negative feedback circuit is configured to provide a variable resistance value to determine a negative feedback gain based on each of the separate gain modes.

An operational amplifier includes: a first amplifier stage, configured to generate first output voltages according to first input voltages; a second amplifier stage, configured to generate second output voltages according to the first output voltages; a second output stage circuit, configured to replicate an equivalent or a scaled-down version of the first output stage circuit; a first common-mode feedback circuit, configured to keep an output common-mode voltage of the second output stage circuit at a predetermined value; a logic loop circuit configured to, when the operational amplifier operates in a direct current calibration phase, adjust a difference between the first output voltages; a bias circuit, configured to generate a voltage close to a common-mode voltage of the first output voltages produced after the operational amplifier is turned on, the voltage serving as a reference voltage of a second common-mode feedback circuit.