A power amplifier circuit includes a first transistor configured to receive a first signal at a base, amplify the first signal, and output a second signal from a collector; and a bias circuit configured to supply a bias current to the base of the first transistor. The bias circuit includes a second transistor configured to supply a bias current to the base of the first transistor, a third transistor including a base connected to a base of the second transistor and a collector connected to a collector of the second transistor, and a fourth transistor including a base connected to an emitter of the third transistor and a collector connected to an emitter of the second transistor and configured to draw at least part of the bias current.

A low noise amplifier (LNA) includes a first transistor and a second transistor. A source of the second transistor is connected to a drain of the first transistor. The LNA further includes a feedback transformer. A gate of the first transistor is connected to a primary winding of the feedback transformer and a gate of the second transistor is connected to a secondary winding of the feedback transformer.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

A transmission module includes n oscillator modules and a phase command signal generator. Each of the oscillator modules includes a voltage controlled oscillator and an amplification circuit. The voltage controlled oscillators output transmission high-frequency signals having the same frequency and synchronized among the n oscillator modules by synchronous control based on a common reference signal. The amplification circuits each perform power amplification for the transmission high-frequency signal from a corresponding one of the voltage controlled oscillators and output the resultant signal. Phases of the transmission high-frequency signals synchronized among the n oscillator modules and output from the voltage controlled oscillators are separately controlled according to respective n phase command signals from the phase command signal generator.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.

An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.

The present invention relates to a method, of providing adaptive impedance in a Power Amplifier (PA), by providing more than one transistors in which one transistor is used to change the load line or to linearize the input signal by adapting the biasing of each transistor, wherein the transistors are connected in parallel.

Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.