Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a differential amplifier connectable to receive the first electrical supply level, the differential amplifier having a first input connectable to a first node of the reference device and a second input connectable to receive a reference electrical level, the differential amplifier arranged to maintain a first electrical level on the first node of the reference device as a function of the reference electrical level.

An amplification device includes a first amplifier configured to amplify an input signal in accordance with a first gate voltage, and a second amplifier configured to amplify the input signal in accordance with a second gate voltage, wherein at least one of the first gate voltage and the second gate voltage are controlled on the basis of a current ratio of a first drain current of the first amplifier to a second drain current of the second amplifier.

An amplification circuit has a field effect transistor, an input side matching circuit, an output side matching circuit, a capacitor, and a resistor. The input side matching circuit is connected between an input port and the source terminal of the field effect transistor and outputs an input signal that changes with a bias voltage as a center value. The output side matching circuit is connected between an output port and the drain terminal of the field effect transistor. The capacitor is connected between the gate terminal of the field effect transistor and a first reference voltage source. The resistor is connected between the gate terminal of the field effect transistor and the first reference voltage source.

A power amplifier arrangement comprises a power amplifier comprising at least one transistor having a first gate and a second gate. The first gate is configured to receive a radio frequency input signal superimposed with a first control signal, and the second gate is configured to receive a second control signal. The first control signal is a linearization signal varying in relation to an envelope of the input signal and the second control signal is a temperature compensation signal varying in relation to a temperature of the power amplifier, or vice versa.

An amplifier system having: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier where the output power is inhibited from increasing with increasing input signal power; and a DC current limiting circuit, coupled between a DC power supply and the amplifier, to: supply DC current from the DC power supply that is equal to quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing DC current from the DC power supply above the quiescent current with increasing input signal power until the output signal power reaches the desired compression point level which is lower than that of a stand-alone amplifier without the DC current limiting circuit; and, then limits the current drawn by the amplifier from the DC power supply.

Cascode power amplifier bias circuits suitable for operating across multiple power supply domains are provided. In certain embodiments, a power amplifier system includes a cascode power amplifier and a multi-domain bias circuit that generates at least a first cascode bias voltage for the cascode power amplifier. The multi-domain bias circuit includes a coarse regulator that generates a regulated voltage based on a power supply voltage that is operable with multiple voltage levels associated with different power supply domains, a bandgap reference circuit that is powered by the regulated voltage and outputs a bandgap reference voltage, a bias voltage generator that generates multiple selectable bias voltages based on the bandgap reference voltage, and a bias voltage selector that chooses the first cascode bias voltage from amongst the selectable bias voltages.

A current reuse FET amplifier according to the present invention provides an effect of reducing a variation of bias current of the amplifier, with gate voltage or a resistor for self-biasing of an FET of the amplifier changing in accordance with a process variation of saturation current Idss of the FET.

A power amplification circuit that includes: a capacitor element in which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer are sequentially stacked, the capacitor element including a first capacitor in which the first metal layer serves as one electrode thereof and the second metal layer serves as another electrode thereof, and a second capacitor in which the second metal layer serves as one electrode thereof and the third metal layer serves as another electrode thereof; and a transistor that amplifies a radio-frequency signal. The radio-frequency signal is supplied to the one electrode of the first capacitor. The other electrode of the first capacitor and the one electrode of the second capacitor are connected to a base of the transistor, and the other electrode of the second capacitor is connected to the emitter of the transistor.

The embodiments described herein include amplifiers configured for use in radio frequency (RF) applications. In accordance with these embodiments, the amplifiers are implemented to generate a shaped envelope signal, and to apply the shaped envelope signal to transistor gate(s) of the amplifier to provide gate bias modulation. So configured, the shaped envelope signal may facilitate high linearity in the amplifier.

An audio reproduction apparatus is shown and includes an amplifier with a power amplification stage having transistors in a push-pull arrangement. A bias generator biases the transistors with a standing current. A processor receives a data stream comprising digital samples of an analog audio signal and analyzes the peak level of each group. It then determines the appropriate standing currents to maintain Class A operation of the power amplification stage given the peak levels of each of the groups. A digital to analog converter produces an analog input signal for the input stage of the amplifier from the data stream. A feedforward path between the processor and the bias generator allows the standing current to be adjusted prior to the arrival of the analog input signal in the power amplification stage.