A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.

A radio frequency signal transmission circuit includes a direct current blocking unit, a biasing impedance circuit, and a radio frequency element. The direct current blocking unit has a first terminal for receiving an input signal, and a second terminal coupled to a first bias voltage terminal. The biasing impedance circuit has a first terminal coupled to the first bias voltage terminal for providing a first bias voltage, and a second terminal coupled to a second bias voltage terminal for receiving a second bias voltage. The radio frequency element is coupled to the first bias voltage terminal, and receives and processes the input signal. When the biasing impedance circuit operates in a first mode, the biasing impedance circuit provides a first impedance. When the biasing impedance circuit operates in a second mode, the biasing impedance circuit provides a second impedance greater than the first impedance.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Bias networks for amplifiers are disclosed. An example bias network includes an adaptive bias circuit, configured to generate a bias signal for an amplifier, and further includes a coupling circuit, configured to couple the adaptive bias circuit to the amplifier. The coupling circuit is made adaptive in that its' impedance depends on a power level of an input signal to be amplified by the amplifier. By configuring the coupling circuit to have a variable impedance that depends on the power level of the input signal, the coupling circuit may adapt to the input power level and, thereby, may modify the bias signal to reduce/optimize at least some of the nonlinearity that may be introduced to the bias signal by the adaptive bias circuit.

A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

An apparatus includes an amplifier and a bias network. The amplifier generally has a predefined linear range. The bias network is generally connected to an input of the amplifier. The bias network generally comprises a linearizer configured to provide gain expansion and extend linearity of the amplifier beyond the predefined linear range.

A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

Systems and methods for amplifying an input signal include amplifier circuitry, an itail connection coupled between a positive voltage circuitry and the negative voltage circuitry and operable to generate an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn), a first resistor rgp disposed to receive the itail voltage and a first voltage corresponding to Vp, and a second resistor rgn disposed to receive the itail voltage and a second voltage corresponding to Vn. A first current output node is coupled to the output of rgp and operable to output a positive output current (Ioutp) corresponding to the current flowing through rgp, and a second current output is coupled to the output of rgn and operable to output a negative output current (Ioutn) corresponding to the current flowing through rgn.