Patent classifications
H03F2200/216
System and Method for Biasing an RF Circuit
In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.
Fully integrated low-noise amplifier
A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.
BIAS CIRCUIT AND POWER AMPLIFIER CIRCUIT
A bias circuit and a power amplifier circuit are provided in the present disclosure. The bias circuit includes an output node, a power detecting circuit, a first constant voltage bias circuit, and a constant current bias circuit. The output node is configured to provide a bias signal to a power amplifier unit. The output node is further configured to receive an input signal of the power amplifier unit. The power detecting circuit is configured to detect a power of the input signal of the power amplifier unit to provide a first control signal. The first constant voltage bias circuit is configured to selectively provide a first signal to the output node according to the first control signal. The constant current bias circuit provides a second signal to the output node.
MULTI-MODE ENVELOPE TRACKING AMPLIFIER CIRCUIT
A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.
RF AMPLIFIER WITH CONDUCTOR-LESS REGION UNDERLYING FILTER CIRCUIT INDUCTOR, AND METHODS OF MANUFACTURE THEREOF
An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.
Low-noise amplifier, folded low-noise amplifier and amplifier circuit module
A low-noise amplifier (LNA), a folded low-noise amplifier (folded LNA) and an amplifier circuit module are provided. The LNA includes a plurality of radio frequency (RF) input stages, at least one bias transistor and at least one radio frequency (RF) output stage. The bias transistor is connected to the RF input stages to provide a DC bias source to one of the RF input stages for isolating others of the RF input stages. The RF output stage is connected in parallel with the RF input stages, which share an adjustable input inductor.
METHOD FOR IMPROVING LINEARITY OF RADIO FREQUENCY POWER AMPLIFIER, COMPENSATION CIRCUIT AND COMMUNICATIONS TERMINAL
A method for improving the linearity of a radio frequency power amplifier, a compensation circuit (307) for implementing the method, and a communications terminal with the compensation circuit (307). In the method, a compensation circuit (307) is connected between a base (a3) and a collector (b3) of a transistor of a common emitter amplifier (306), in order to neutralize the impact of a variation in capacitance between the base (a3) and the collector (b3) of the transistor (306) according to a radio frequency signal. No additional direct-current power consumption is needed, and degradation in performance of other radio frequency power amplifiers can be avoided. The corresponding compensation circuit (307) can be easily integrated with a main amplification circuit, without affecting other performance of the main amplification circuit, and provides high adjustability.
Multi-mode envelope tracking amplifier circuit
A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.
Compact architecture for multipath low noise amplifier
Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.
Amplifier and signal processing apparatus
An amplifier includes a P-type transistor and an N-type transistor that are connected in series, an operation amplifier, a transformer, and a variable attenuator. In the operation amplifier, an output terminal is coupled to a gate side of one of the P-type transistor and the N-type transistor, one of an inverting input terminal and a non-inverting input terminal is coupled to drain sides of both of the P-type transistor and the N-type transistor, and a reference voltage is to be applied to the other of the inverting input terminal and the non-inverting input terminal. In the transformer, a primary coil is coupled to a source side of one of the P-type transistor and the N-type transistor. The variable attenuator is provided between a secondary coil and gate terminals of both of the N-type transistor and the P-type transistor.