A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A power amplifier device includes a first amplifier, a second amplifier, a capacitor, a node, and an impedance matching circuit. The second amplifier amplifies a radio frequency signal transmitted from the first amplifier. The capacitor is coupled between an output terminal of the first amplifier and an input terminal of the second amplifier. The node is disposed between the input terminal of the second amplifier and the capacitor. The impedance matching circuit is coupled to the node and a common voltage terminal. The impedance matching circuit is substantially an open circuit at a center frequency of the radio frequency signal. The impedance matching circuit provides substantially a short-circuited path from the node to the common voltage terminal at a frequency twice the center frequency.

A power amplifier includes a distributor distributing an input first signal to a second signal and a third signal delayed by about 2 degrees (45<<90) from the second signal, a first amplifier amplifying the second signal and outputting a fourth signal when a first-signal power level is not lower than a first level, a second amplifier amplifying the third signal and outputting a fifth signal when the first-signal power level is not lower than a second level that is greater than the first level, a first phase shifter receiving the fourth signal and outputting a sixth signal delayed by about degrees from the fourth signal, a second phase shifter receiving the fifth signal and outputting a seventh signal advanced by about degrees from the fifth signal, and a combiner combining the sixth and seventh signals and outputting an amplified signal of the first signal.

Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor with a drain-source capacitance that is relatively low, an input impedance matching circuit, and an input-side harmonic termination circuit. The input impedance matching circuit includes a harmonic termination circuit, which in turn includes a first inductance (a first plurality of bondwires) and a first capacitance coupled in series between the transistor output and a ground reference node. The input impedance matching circuit also includes a second inductance (a second plurality of bondwires), a third inductance (a third plurality of bondwires), and a second capacitance coupled in a T-match configuration between the input lead and the transistor input. The first and second capacitances may be metal-insulator-metal capacitors in an integrated passive device.

Embodiments of an amplifier and method of operating an amplifier are disclosed. In some embodiments, the amplifier includes an active device having an input terminal and an output terminal. A harmonic termination is coupled in shunt with respect to the input terminal or the output terminal, wherein the harmonic termination includes a capacitor-shunt inductor-capacitor or similar network. In this manner, the harmonic terminator shapes the waveform of the RF signal without introducing large amounts of capacitance at the fundamental/center operating frequency.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An envelope detecting circuit is for generating an envelope signal of an input RF signal as described. The envelope detecting circuit includes an input terminal, an output terminal, a balun, a transistor, and an integrating circuit. The transistor, which is operated in the class B or the class C mode, receives an input signal from the balun, amplifies the input signal, and outputs an amplified signal. The integrating circuit, which is provided between the transistor and the output terminal, provides a series circuit of a resistor and a capacitor between the bias supply and ground. The transistor receives the bias through the resistor. The capacitor holds bottom levels of the amplified signal.

A power amplifier includes a distributor distributing an input first signal to a second signal and a third signal delayed by about 2 degrees (45<<90) from the second signal, a first amplifier amplifying the second signal and outputting a fourth signal when a first-signal power level is not lower than a first level, a second amplifier amplifying the third signal and outputting a fifth signal when the first-signal power level is not lower than a second level that is greater than the first level, a first phase shifter receiving the fourth signal and outputting a sixth signal delayed by about degrees from the fourth signal, a second phase shifter receiving the fifth signal and outputting a seventh signal advanced by about degrees from the fifth signal, and a combiner combining the sixth and seventh signals and outputting an amplified signal of the first signal.

Processes and systems for producing glass fibers having regions devoid of glass using submerged combustion melters, including feeding a vitrifiable feed material into a feed inlet of a melting zone of a melter vessel, and heating the vitrifiable material with at least one burner directing combustion products of an oxidant and a first fuel into the melting zone under a level of the molten material in the zone. One or more of the burners is configured to impart heat and turbulence to the molten material, producing a turbulent molten material comprising a plurality of bubbles suspended in the molten material, the bubbles comprising at least some of the combustion products, and optionally other gas species introduced by the burners. The molten material and bubbles are drawn through a bushing fluidly connected to a forehearth to produce a glass fiber comprising a plurality of interior regions substantially devoid of glass.

A semiconductor device that outputs a radio-frequency (RF) signal with high power is disclosed. The semiconductor device includes a housing, a semiconductor chip, an impedance converter, a capacitor, and a bonding wire. The housing includes a heat sink, an output lead terminal, and a bias terminal electrically isolated from the output lead terminal. The semiconductor chip is mounted on the heat sink of the housing. The impedance converter provides an input port, an output port, and an intermediate port between the input port and the output port thereof. The capacitor is mounted on the heat sink and between the impedance converter and the output lead terminal. The bonding wire connects the bias lead terminal with the intermediate port.