Methods and devices for limiting the power level of low noise amplifiers (LNA) implemented in radio frequency (RF) receiver front-ends. The described methods are applicable to bypass, low and high gain modes of the LNA. According to the described methods, the decoder allows the signal to be clamped before or after being attenuated. The benefit of such methods is to improve large signal performances (e.g. IIP3, P1dB) of the RF receiver front-end, while still meeting the clamping requirements, or improve (lower) clamped output power, while still meeting large signal performances (e.g. IIP3, P1dB).

An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.

A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

The present invention includes a current integrator for an organic light-emitting diode (OLED) panel. The current integrator includes an operational amplifier, which includes an output stage. The output stage, coupled to an output terminal of the current integrator, includes a first output transistor, a second output transistor, a first stack transistor and a second stack transistor. The first stack transistor is coupled between the first output transistor and the output terminal. The second stack transistor is coupled between the second output transistor and the output terminal.

Provided are embodiments that include a circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source. The circuit includes an operational amplifier, and a switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier. Also provided are embodiments for a method for operating a circuit in a disabled mode for error reduction.