Patent classifications
H03F2200/243
PROCESS OF USING A SUBMERGED COMBUSTION MELTER TO PRODUCE HOLLOW GLASS FIBER OR SOLID GLASS FIBER HAVING ENTRAINED BUBBLES, AND BURNERS AND SYSTEMS TO MAKE SUCH FIBERS
Processes and systems for producing glass fibers having regions devoid of glass using submerged combustion melters, including feeding a vitrifiable feed material into a feed inlet of a melting zone of a melter vessel, and heating the vitrifiable material with at least one burner directing combustion products of an oxidant and a first fuel into the melting zone under a level of the molten material in the zone. One or more of the burners is configured to impart heat and turbulence to the molten material, producing a turbulent molten material comprising a plurality of bubbles suspended in the molten material, the bubbles comprising at least some of the combustion products, and optionally other gas species introduced by the burners. The molten material and bubbles are drawn through a bushing fluidly connected to a forehearth to produce a glass fiber comprising a plurality of interior regions substantially devoid of glass.
Radio-frequency signal amplifier circuit, power amplifier module, front-end circuit, and communication device
A radio-frequency signal amplifier circuit that is used in a front-end circuit and that propagates a radio-frequency transmission signal and a radio-frequency reception signal is described. The amplifier circuit has an amplifier transistor, a bias circuit, a resistor, and an LC series resonance circuit. The LC series resonant circuit has one end that is connected to a node between the resistor and a signal input terminal, and has another end that is connected to a grounding terminal. A resonant frequency of the LC series resonance circuit is included in a difference frequency band between the frequencies of the transmission signal and the reception signal.
Source switched split LNA
A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.
Power amplifier
A power amplifier includes an amplifying circuit configured to amplify an input signal and comprising transistors, which may be disposed in parallel with one another and divided into a first group of transistors and a second group of transistors. The power amplifier also includes a bias circuit configured to supply bias power to one of the transistors of the first group and the transistors of the second group.
Logarithmic detector amplifier system for use as high sensitivity selective receiver without frequency conversion
A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.
Cascode Amplifier Bias Circuits
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
Digital variable capacitance circuit, resonant circuit, amplification circuit, and transmitter
A radio frequency integrated circuit includes an amplification circuit for outputting a radio frequency signal to an antenna, a balun including a first terminal, a second terminal, a third terminal, and a fourth terminal, and a variable capacitance circuit including a fifth terminal and a sixth terminal. The first terminal and the second terminal of the balun receive output signals of the amplification circuit. The third terminal and the fourth terminal of the balun are connected to the fifth terminal and the sixth terminal of the variable capacitance circuit, respectively, and the fifth terminal is connected to a radio frequency output terminal. The variable capacitance circuit includes a plurality of capacity cells that are connected in parallel between two output terminals.
LNA with programmable linearity
A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
Cascode amplifier bias circuits
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
RADIO-FREQUENCY SIGNAL AMPLIFIER CIRCUIT, POWER AMPLIFIER MODULE, FRONT-END CIRCUIT, AND COMMUNICATION DEVICE
A radio-frequency signal amplifier circuit that is used in a front-end circuit configured to propagate a radio-frequency transmission signal and a radio-frequency reception signal, includes an amplifier transistor configured to amplify the radio-frequency transmission signal, a bias circuit configured to supply a bias to a signal input terminal of the amplifier transistor, a resistor having one end connected to the bias circuit and the other end connected to the signal input terminal, and an LC series resonance circuit that has one end connected to a node n1 between the resistor and the signal input terminal and the other end connected to a grounding terminal. A resonant frequency fr of the LC series resonance circuit is included in a difference frequency band between the radio-frequency transmission signal and the radio-frequency reception signal.