A trans-impedance amplifier (TIA) includes a first circuit, a second circuit, and a third circuit. Both the first circuit and the second circuit are coupled to a current source, an operational amplifier, and the third circuit. The first circuit is configured to receive a first current, provide a third voltage to the third circuit, perform shape filtering on the first current, and convert the shape filtered first current to a first voltage for output. The second circuit is configured to receive a second current, provide a fourth voltage to the third circuit, perform shape filtering on the second current, and convert the shape filtered second current to a second voltage for output. The third circuit is configured to cooperate with the first circuit and the second circuit in performing shape filtering. The operational amplifier is configured to provide a small-signal virtual ground point to the first circuit.

The present disclosure relates to Class D amplifier circuitry comprising a mode controller configured to dynamically adjust an operational switching mode of the Class D amplifier over a range between a Class AD mode and a Class BD mode.

A device includes an amplifier having inverting and non-inverting inputs and an output. The device includes a capacitor coupled to a first node and to ground, a resistor coupled to the first node and the amplifier output, and a first switch coupled to the first node and a current sink, which is coupled to ground. The device includes AND gate having inputs and an output coupled to control terminal of first switch. The device includes a first comparator having non-inverting and inverting inputs and an output coupled to an AND gate input; a second comparator having a non-inverting input coupled to the amplifier output, an inverting input coupled to a transistor stack, and an output coupled to an AND gate input; and a second switch coupled to the transistor stack and to a current source, the second switch having a control terminal coupled to the first comparator output.

A low-noise amplifier is disclosed having a first transistor with a first current terminal coupled to a supply voltage rail through a load resistor and a second current terminal coupled to an input node, wherein a bias resistor is coupled between the input node and a fixed voltage node. A second transistor has a third current terminal coupled to an output node and a fourth current terminal coupled to the fixed voltage node. A feedback capacitor is coupled between the input node and the output node, wherein capacitance of the feedback capacitor is sized to eliminate the need for coupling an input impedance matching inductor to the input node.

A single printed-circuit board of a class-D amplifier includes an input ground, an output ground, an input amplifying circuit, a modulation circuit, an output amplifying circuit, and an output filter, a solid pattern, a first feedback circuit, and a second feedback circuit. The solid pattern of the output ground extends into all regions of the input amplifying circuit, the modulation circuit, the output amplifying circuit and the output filter. The first feedback circuit executes a feedback where a voltage at a first connecting point is negatively fed back to an inverting input of the input amplifying circuit. The second feedback circuit executes a feedback where a voltage at a second connecting point is negatively fed back to a non-inverting input of the input amplifying circuit.

A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.

An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit with a first inductor and a first capacitance in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a shunt-L circuit. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitance in series between the amplifier output and ground. The shunt-L circuit includes a fourth inductor and a third capacitance connected in series between the amplifier output and ground. The input-side and output-side harmonic termination circuits resonate at a harmonic frequency of a fundamental frequency of operation of the amplifier.

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

An amplifier includes a first input circuit, a second input circuit, a first compensation circuit, a second compensation circuit. The first input circuit changes a voltage level of the negative output node based on a first input signal. The second input circuit changes a voltage level of the positive output node based on a second input signal. The first compensation circuit changes the voltage level of the positive output node based on the first input signal. The second compensation circuit changes the voltage level of the negative output node based on the second output signal.

A bandpass parametric amplifier circuit includes a plurality of unit cells. At least one unit cell includes a first inductor having a first node coupled to a center conductor and a second node coupled to ground. There is a first capacitor having a first node coupled to the center conductor and a second node coupled to ground. There is a second inductor having a first node coupled to the center conductor. A second capacitor has a first node coupled to a second node of the second inductor. The second capacitor and the second inductor are in series with the center conductor.