A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit is an output pre-match impedance conditioning shunt circuit, which includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The first shunt inductance comprises a plurality of bondwires coupled between the first current carrying terminal and the second shunt inductance, and the second shunt inductance comprises an integrated inductor coupled between the first shunt inductance and a first terminal of the shunt capacitor. The shunt capacitor is configured to provide capacitive harmonic control of an output of the transistor.

A device includes a substrate and a package input terminal. The device includes a driver amplifier mounted to the substrate and configured to receive a radio frequency input signal. A first amplifier is mounted to the substrate. The first amplifier includes a first amplifier input terminal. A second amplifier is mounted to the substrate. The second amplifier includes a second amplifier input terminal. An inter-stage network is connected between the driver amplifier and the first amplifier and between the driver amplifier and the second amplifier. The inter-stage network includes a first capacitor connected between the driver amplifier and the first amplifier input terminal, and an inductor having a first terminal and a second terminal. The first terminal of the inductor is connected to the first capacitor. The inter-stage network includes a second capacitor connected between the second terminal of the inductor and the second amplifier input terminal.

Apparatus and methods for quadrature combined Doherty amplifiers are provided herein. In certain embodiments, a separator is used to separate a radio frequency (RF) input signal into a plurality of input signal components that are amplified by a pair of Doherty amplifiers operating in quadrature. Additionally, a combiner is used to combine a plurality of output signal components generated by the pair of Doherty amplifiers, thereby generating an RF output signal exhibiting quadrature balancing.

Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.

A circuit arrangement for an MRT system and a method for operating an MRT system are disclosed. The circuit arrangement includes a gradient amplifier having a switch-mode output stage, a regulator device, and a modulator connected therebetween in the circuit. To ensure patient safety, a control path is integrated into a drive path of the circuit arrangement or the MRT system provided for driving a gradient coil, the gradient coil being connected to an output of the switch-mode output stage. The control path includes a limiter stage connected downstream of the regulator device, the modulator, the switch-mode output stage and its supply voltage. The limiter stage is connected in the circuit between the regulator device and an input of the modulator, to limit a control signal output by the regulator device and limit the voltage for the gradient coil provided by the switch-mode output stage at its output.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A low noise amplifier and a radio frequency amplification method using the low noise amplifier are provided. The low noise amplifier includes gain stage circuits, the number of which is not less than that of RF signals to be amplified, and the gain stage circuit is configured to independently amplify the RF signal when being enabled; a plurality of amplification selection switching circuits, each of which is connected to one of the gain stage circuits and is configured to, according to the RF signal, control the gain stage circuit to be enabled or disabled; a plurality of driving circuits, each of which is connected to a respective one of the plurality of gain stage circuits and is configured to, when the gain stage circuit is enabled, receive at least one RF signal amplified by the gain stage circuit and output the amplified RF signal; and at least one load circuit.