Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A chopper amplifier and method of operation are described. The chopper amplifier comprises a first chopper arranged to modulate an input signal using a first chopper signal having a chopper frequency. An amplification stage has an input arranged to receive the chopped signal and an output, and supplies an amplified signal at the output. An output chopper is arranged to integrate the amplified signal using a second chopper signal having the chopper frequency to generate an amplified output signal. The amplification stage is further configured to filter the chopped signal to attenuate signal components having frequencies lower than the chopper frequency.

A power amplifier including: a main power amplification device having an output; an auxiliary power amplification device having an output; a load modulation circuit operably connected to the output of the main power amplification device and the output of the auxiliary power amplification device; and a post-matching circuit operably connected to load modulation circuit. The load modulation circuit is arranged to enable fundamental frequency load modulation and to enable modulated harmonic terminations of at least the second and third harmonic frequencies. The modulated harmonic terminations may include drain terminations.

A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting. To reduce distortion and more particularly, total harmonic distortion (THD), the amplifier output stage includes a substantially linear circuit configured to provide a bidirectional current sink for residual currents from the load occurring during at least part of each dead time interval.

A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A power amplifier circuit includes an amplifier transistor which amplifies a radio frequency signal applied to its base and outputs the amplified signal; a resistance element having a first end, and a second end electrically connected to the base of the amplifier transistor; a first bias transistor having a collector to which a first voltage is applied, a base to which a first bias voltage is applied, and an emitter electrically connected to the first end of the resistance element and which supplies a bias current to the base of the amplifier transistor through the resistance element; and a second bias transistor having an emitter electrically connected to the emitter of the first bias transistor and the first end of the resistance element, a base to which a second bias voltage is applied, and a collector to which a second voltage lower than the first voltage is applied.

A semiconductor device including a radio-frequency amplifier circuit and a band selection switch is mounted on or in a module substrate. An output matching circuit coupled between the radio-frequency amplifier circuit and the band selection switch is on or in the module substrate. The semiconductor device includes a first member at which the band selection switch having a semiconductor element made of an elemental semiconductor is formed and a second member joined to the first member in surface contact therewith. The radio-frequency amplifier circuit including a semiconductor element made of a compound semiconductor is formed at the second member. Conductive protrusions are raised from first and second members. The semiconductor device is mounted on or in the module substrate with the conductive protrusions interposed therebetween, and in plan view, is in close proximity to the output matching circuit or overlaps a passive element constituting the output matching circuit.

A tunable vector recombination amplifier comprises an input, an output, first and second amplifier circuit paths each including a respective phase shifter to receive a respective input signal from the input and to apply a respective phase shift to produce a respective phase-shifted signal, a respective interstage impedance matching network, and a respective amplifier connected between the respective phase shifter and interstage impedance matching network to receive and amplify the respective phase-shifted signal to produce a respective amplified signal, first and second controllable DC voltage sources each coupled to a respective amplifier and configured to provide a respective supply voltage to the respective amplifier, values of the supply voltages being independently controllable, and an output amplifier stage to receive, amplify, and vectorially combine the amplified signals to produce a combined signal having a specified phase determined by the phase shifts and supply-voltage values and a specified amplitude at the output.