A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A power splitter that amplifies an input radio-frequency (RF) signal. The power splitter uses a single transistor in a common emitter stage of a cascode amplifier and two or more common base stages of the cascode amplifier to amplify and to split the input RF signal. A common base biasing signal can be used to simultaneously enable two or more of the common base stages to generate two or more amplified RF output signals.

A low noise amplifier and a radio frequency amplification method using the low noise amplifier are provided. The low noise amplifier includes gain stage circuits, the number of which is not less than that of RF signals to be amplified, and the gain stage circuit is configured to independently amplify the RF signal when being enabled; a plurality of amplification selection switching circuits, each of which is connected to one of the gain stage circuits and is configured to, according to the RF signal, control the gain stage circuit to be enabled or disabled; a plurality of driving circuits, each of which is connected to a respective one of the plurality of gain stage circuits and is configured to, when the gain stage circuit is enabled, receive at least one RF signal amplified by the gain stage circuit and output the amplified RF signal; and at least one load circuit.

Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.

The present disclosure discloses a dynamic amplification circuit, including: a first drive circuit, receives a first control signal to generate a first and a second voltage signal; a second drive circuit, receives the first and the second voltage signal to generate a first drive signal; a third drive circuit, receives the first control signal and the first drive signal to generate a second control signal; and a dynamic amplifier DA, controls a first and a second control switch according to the control signals; in a first time period, the first control signal is high level, the second control signal is low level; in a second time period, the opposite is the case; in a third time period, the first and the second control signal are both at low level, a duration of the second time period is inversely proportional to a transconductance of a transistor in a saturation region.

Multiband power amplifier with cascode switching. A power amplification system can include a first transistor having a base configured to receive an input radio-frequency (RF) signal and having an emitter coupled to a ground potential. The power amplification system can include a plurality of second transistors. Each one of the plurality of second transistors can have a respective emitter coupled to a collector of the first transistor and can be configured to, when biased at a respective base, output an output RF signal at a respective collector. The power amplification system can further include a biasing circuit configured to bias one or more of the plurality of second transistors based on a control signal.

A current mirror device includes an input end for receiving an input signal, an output end for outputting an amplified signal of the input signal, first through third transistors, and an operational amplifier. The first transistor includes a first end coupled to first reference current and a second end coupled to a bias voltage. The control end of the second transistor is coupled to the input end. The third transistor includes a first end coupled to the output end, a second end coupled to the first end of the second transistor and a control end coupled to a reference voltage. The operational amplifier is configured to keep a first voltage and a second voltage at substantially the same level, wherein the first voltage is obtained on the first end of the first transistor and the second voltage is obtained on the first end of the second transistor. Therefore, the reference current flowing through the first transistor can be accurately amplified to a desired value and mirrored to become load current flowing through the second transistor.

An output circuit includes a first transistor, a second transistor, an operational amplifier that outputs a control voltage, and a switch circuit that controls voltage output in accordance with a control signal. When the control signal is in a first state, the switch circuit supplies the control voltage to the gate of the first transistor to turn on the first transistor and electrically connects the drain of first transistor to the operational amplifier so that a first output voltage is output from the drain of the first transistor. When the control signal is in a second state, the switch circuit supplies the control voltage to the gate of the second transistor to turn on the second transistor and electrically connects the drain of the second transistor to the operational amplifier so that a second output voltage is output from the drain of the second transistor.

Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.

A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting. To reduce distortion and more particularly, total harmonic distortion (THD), the amplifier output stage includes a substantially linear circuit configured to provide a bidirectional current sink for residual currents from the load occurring during at least part of each dead time interval.