Amplifiers, amplification circuits, and phase shifters, for example, for flexibly adjusting an output phase to thereby meet a requirement of a constant phase on a link in a communications field, are provided. In one aspect, an amplifier includes first, second, and third MOS transistors. The first MOS transistor includes a gate separately coupled to a signal input end and a bias voltage input end, a source coupled to a power supply, and a drain separately coupled to sources of the second and third MOS transistors. A drain of the third MOS transistor is coupled to a ground, and a drain of the second MOS transistor is coupled to a signal output end. The bias voltage input end is configured to receive a bias voltage to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end.

Provided is a high-gain amplifier based on double-gain boosting including a first gain amplification unit including a first amplifier, a second amplifier, and a an interstage matching network connected between the first amplifier and the second amplifier and performing primary amplification; and a second gain amplification unit connected in parallel with the first gain amplification unit and performing secondary boosting.

A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second transistors (e.g., main and peaking transistors) with first and second output terminals, respectively, all of which is integrally-formed with a semiconductor die. A signal path through the second transistor extends in a direction from a control terminal of the second transistor to the second output terminal, where the second output terminal corresponds to or is closely electrically coupled to a combining node. The amplifier also includes an integrated phase delay circuit that is configured to apply an overall phase delay (e.g., 90 degrees) to a signal carried between the first and second output terminals. The integrated phase delay circuit includes delay circuit wirebonds coupled between the first and second output terminals, and the delay circuit wirebonds extend in a third direction that is angularly offset from (e.g., perpendicular to) the second direction.

A dual-band MMIC power amplifier and method of operation to amplify frequencies in different RF bands while only requiring input drive signals at frequencies f.sub.1 and f.sub.2 in a narrow RF input band. This allows for the use of a conventional narrowband RF IC to drive the MMIC and does not require additional circuitry (e.g., a LO) on the MMIC power amplifier. The matching network of the last amplification stage is modified to pass f.sub.1 (or a harmonic thereof), reflect f.sub.2, pass a P.sup.th harmonic of f.sub.2 where P is 2 or 3 and to reflect any unused 1.sup.st, 2.sup.nd or 3.sup.rd order harmonics of f.sub.1 or f.sub.2 back into the MMIC. In response to an input signal at f.sub.1, the MMIC power amplifier amplifies and outputs a signal at f.sub.1 (or a harmonic thereof). In response to an input signal at f.sub.2 at sufficient RF power, the last amplification stage operates in compression such that the MMIC power amplifier generates the harmonics, selects the P.sup.th harmonic and outputs an amplified RF signal at P*f.sub.2.

The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.

The wireless RF semiconductor system is described for use in wireless communication devices that operate in frequency range from approximately 6 GigaHertz (GHz) to 100 GHz. The system comprises of at least one RF antenna and at least one RF integrated circuit fabricated (or built) on the same semiconductor substrate inside a one single packaged module. The wireless RF semiconductor system is described in a variety of different configurations with its functionality divided up over several single chip circuits. The system simplifies assembly, reduces size and cost, and allows for a quick time to market, while maximizing the RF performance demanded by fixed and mobile 4G, 5G and other wireless standards. The system uses a novel idea of configuration and packaging of active and passive RF components into a single module. This in turn allows RF manufacturers to unlock the potential of very high frequencies operation that were previously thought too expensive and unattainable to average user. The wireless RF semiconductor system can be implemented in both mobile solutions (such as phones and tablets) and fixed applications (such as repeaters, base-stations, and distributed antenna systems).

Provided is an amplification circuit that includes: a low-noise amplifier that includes an FET as an amplification element and that amplifies a radio-frequency signal inputted to the gate of the FET; an input matching network that matches the input impedance of the low-noise amplifier; and a switch that is serially connected between ground and a node on a line connecting the input matching network and the gate of the FET to each other.

Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.

A matching circuit structure for effectively suppressing the low-frequency clutter of a power amplifier of a mobile phone, falling within the technical field of radio frequency Pas is provided. The circuit structure includes an input end, a blocking capacitor, a power amplifier (PA), an output matching network and an output end connected in series; and the matching circuit structure further includes a negative feedback network connected in parallel to a transmission end of the PA; the negative feedback network includes a resonant capacitor, a resonant inductor and a matching inductor; the resonant capacitor and the resonant inductor are connected in parallel to form a frequency selecting network, and the frequency selecting network is connected in series with the matching inductor and to the ground. The matching circuit structure above can be used to effectively suppress the low-frequency clutter of a power amplifier.