Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a mobile device includes a supply control circuit that controls a voltage of a supply network, a plurality of radio frequency circuits that receive power from the supply network and are selectively enabled by a plurality of enable signals, a plurality of switchable capacitors electrically connected to the supply network, a plurality of field-effect transistors operatively associated with the plurality of switchable capacitors, and a bias control circuit that generates a plurality of control signals that bias the plurality of field-effect transistors based on a state of the plurality of enable signals. Each of the plurality of control signals are operable to selectively bias a corresponding one of the plurality of field-effect transistors in a cutoff mode to provide high impedance or as a dampening resistor to suppress oscillations.

A receiver is provided to support a plurality of carrier aggregation modes. The receiver includes a low-noise amplifier (LNA) module including a plurality of LNAs, wherein the LNAs are arranged to receive input signals from a plurality of input ports, respectively, and each of the LNAs generates and outputs a plurality of noise-cancelled signals at a plurality of output terminals of the LNA module.

A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F.sub.2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Apparatus and methods for multi-mode power amplifiers are provided herein. In certain configurations, a wireless device includes a multi-mode power amplifier including a plurality of amplification paths electrically connected in parallel with one another. The plurality of amplification paths includes a first amplification path including an input stage of a first stage type and an output stage of a second stage type, and a second amplification path including an output stage of the second stage type. The first stage type provides non-inverting gain and the second stage type provides inverting gain. The wireless device further includes a transceiver that provides a radio frequency signal to the multi-mode power amplifier, and that operates the multi-mode power amplifier in a selected power mode chosen from a plurality of power modes based on selectively activating one or more of the plurality of amplification paths.

A power amplifier circuit includes: a first branch, including a first amplifier and a first matching network cascaded; a second branch, including a second amplifier and a second matching network cascaded, where a first coupled line enables the first branch and the second branch to form a first combiner; a third branch, including a third amplifier and a third matching network cascaded; and a fourth branch, including a fourth amplifier and a fourth matching network cascaded, where a second coupled line enables the third branch and the fourth branch to form a second combiner. A first output end of the first coupled line is a signal output end of the circuit, and a second output end of the first coupled line is connected to a first output end of the second coupled line, to enable the first combiner and the second combiner to form a series combiner.

Disclosed herein are power amplification (PA) systems configured to amplify a signal, such as a radio-frequency signal. The PA system includes a plurality of power amplifiers that are configured to amplify a signal received at a signal input and to output the amplified signal at a signal output. The power amplifiers are configured to receive a supply voltage that is a combination of a battery voltage and an envelope tracking signal. The PA system includes a PA controller configured to control the power amplifiers based at least in part on the battery voltage or a power output of the power amplifiers. The PA controller can be configured to alter impedance matching components of the PA system to reconfigure a load line of the power amplifiers.

A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.

A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.

A power amplification circuit includes: a first amplifier that is input with a first signal and outputs a second signal; a bias circuit that supplies a bias current or voltage to the first amplifier; and a control voltage generating circuit that generates a control voltage in accordance with the first signal. The bias circuit includes a first transistor that outputs the bias current or voltage, a second transistor provided between the emitter or source of the first transistor and ground, and a third transistor that is supplied with the control voltage and that supplies a first current or voltage to the second transistor. The value of the first current or voltage when the signal level is a first level is larger than the value of the first current or voltage when the signal level is a second level. The first level is higher than the second level.