An amplifier includes: a signal polarity inversion circuit which modulates an input signal and outputs a modulation signal; an amplifier circuit which is constituted from an operational transconductance amplifier (OTA) to amplify the modulation signal and output a current; and a sample-hold circuit having a sampling capacitor which is charged and discharged by selective sampling of the output current of the amplifier circuit and a holding capacitor to which the voltage of the sampling capacitor is transferred.

In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal. Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier.

A radar system includes a transmitter circuit, which transmits a radar wave having a chirp frequency gradually increasing or decreasing to a target, and a frequency conversion circuit, which demodulates a signal of the radar wave reflected at the target by frequency-conversion in correspondence to the chirp frequency. A radar signal processor includes a variable amplifier connected to an output side of the frequency conversion circuit, and a feedback circuit which detects an output of the variable amplifier as a detection signal and feeds back a signal of a frequency band included in the detection signal to an input of the variable amplifier. The feedback circuit is configured to cut off and not cut off a frequency band including a DC offset transient response frequency, which occurs at time of frequency conversion by the frequency conversion circuit, during a specified period and a period other than the specified period, respectively. The specified period is a predetermined first period from starting of a demodulation operation of the frequency conversion circuit and/or a predetermined second period from ending of the demodulation operation of the frequency operation of the frequency conversion circuit.

An inductor is provided, comprising: a first ferrite core piece and a second ferrite core piece, each of which are made of substantially similar materials, exhibit desired electromagnetic properties, and which are fashioned in a substantially similar manner and shape, and wherein each of the first and second ferrite core pieces comprises a substantially planar mating surface, a center post, and a wire core assembly channel, and wherein a first substantially planar mating surface of the first ferrite core piece is adapted to planarly mate with a second substantially planar mating surface of the second ferrite core piece; and a wire core assembly adapted to be substantially self-locating and self-centering about a first or second center post when located in a respective first or second wire core assembly channel.

An apparatus includes an amplifier, an input port, a first modulator circuit connected to the input port, and a correction circuit. The correction circuit is configured to determine a common mode voltage of the input port and receive a first clock signal. The correction circuit is further configured to manipulate, based at least in part upon the common mode voltage of the input port, the first clock signal to generate a second clock signal. The second clock signal is produced for the first modulator circuit. The correction circuit is further configured to determine whether the second clock signal is out of phase with a third clock signal, and, based upon a determination that the second clock signal is out of phase with the third clock signal, reset the second clock signal.

An inductor is provided, comprising: a first ferrite core piece and a second ferrite core piece, each of which are made of substantially similar materials, exhibit desired electromagnetic properties, and which are fashioned in a substantially similar manner and shape, and wherein each of the first and second ferrite core pieces comprises a substantially planar mating surface, a center post, and a wire core assembly channel, and wherein a first substantially planar mating surface of the first ferrite core piece is adapted to planarly mate with a second substantially planar mating surface of the second ferrite core piece; and a wire core assembly adapted to be substantially self-locating and self-centering about a first or second center post when located in a respective first or second wire core assembly channel.

Certain aspects of the present disclosure are directed to a digital predistortion (DPD) device for use within a wireless transmitter that permits the use of a downstream digital-to-analog converter that operates at a clock rate close to the bandwidth of a digital baseband input signal. In some examples, a sampling rate of a digital baseband input signal is increased using an upsampler to obtain an increased rate digital input signal. Predistortion is applied to the increased rate digital input signal using a DPD device to obtain a predistorted digital signal. The sampling rate of the predistorted digital signal is then decreased using a downsampler to obtain a lower-rate predistorted digital signal with a sampling rate below the increased rate of the upsampler (e.g. close to the bandwidth of a digital baseband input signal). A low pass filter may be provided to filter out-of-band signal components from the predistorted digital signal.

A class D audio amplifier includes a modulator for receipt of an audio signal and converting the audio signal into a modulated audio signal having a predetermined carrier frequency. The class D audio amplifier additionally includes an output stage having a plurality of power transistors coupled in cascade between a first DC supply voltage and a second DC supply voltage, and a plurality of gate drivers configured to generate respective modulated gate drive signals to the plurality of power transistors. A controller is configured to adjust a level of a first modulated gate drive signal applied to a first power transistor of the output stage based on a level of the audio signal.

In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal. Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier.

In one example, a method includes: at a beginning of a packet communication, setting a maximum gain setting for a plurality of gain components of a receiver; and during a preamble portion of the packet communication, reducing a gain setting for one or more of the plurality of gain components in response to at least one of a first signal output by a first component of the receiver being greater than a first threshold and a second signal output by a second component of the receiver being greater than a second threshold.