A radio frequency receiver comprises a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor. The circuit further includes a bias feedback network that includes a bias transistor and a resistive network that consists of only resistive elements such that no inductors and no capacitors are provided within the bias feedback network.

Disclosed are an apparatus and method of processing an audio signal to optimize audio for a room environment. One example method of operation may include recording the audio signal generated within a particular room environment and processing the audio signal to create an original frequency response based on the audio signal. The method may also include identifying a target sub-region of the frequency response which has a predetermined area percentage of a total area under a curve generated by the frequency response, determining whether the target sub-region is a narrow energy region, creating a filter to adjust the frequency response, and applying the filter to the audio signal.

The embodiments described herein provide inverse class F (class F.sup.1) amplifiers. In general, the inverse class F amplifiers are implemented with a transistor, an output inductance and a transmission line configured to approximate inverse class F voltage and current output waveforms by compensating the effects of the transistor's intrinsic output capacitance for some even harmonic signals while providing a low impedance for some odd harmonic signals. Specifically, the transistor is configured with the output inductance and transmission line to form a parallel LC circuit that resonates at the second harmonic frequency. The parallel LC circuit effectively creates high impedance for the second harmonic signals, thus blocking the capacitive reactance path to ground for those harmonic signals that the intrinsic output capacitance would otherwise provide. This facilitates the operation of the amplifier as an effective, high efficiency, inverse class F amplifier.

A compound semiconductor device includes a compound semiconductor stacked structure, the compound semiconductor stacked structure including: an electron transit layer; an electron supply layer formed above the electron transit layer, the electron supply layer containing an n-type impurity; and a cap layer formed above the electron supply layer and containing the n-type impurity, in which in the electron supply layer, a concentration of the n-type impurity contained therein is non-uniform in a film thickness direction and a concentration of the n-type impurity in a surface of the cap layer side is lower than a maximum concentration of the n-type impurity in the electron supply layer.

Pulse shaping biasing circuitry includes square wave generator circuitry, first inverse ramp signal generator circuitry, and second inverse ramp signal generator circuitry. The square wave generator circuitry is coupled between an input node and signal summation circuitry, and is configured to generate a square wave signal. The first inverse ramp signal generator circuitry is coupled in parallel with the square wave generator circuitry and configured to generate a first inverted ramp signal. The second inverse ramp signal generator circuitry is coupled in parallel with the square wave generator circuitry and the first inverse ramp signal generator circuitry and configured to generate a second inverted ramp signal. The square wave signal, the first inverted ramp signal, and the second inverted ramp signal are combined by the signal summation circuitry to provide a pulse shaping bias signal for a radio frequency (RF) power amplifier.

Features and advantages of the present disclosure include a multimode voltage controlled oscillator (VCO). In one embodiment, a circuit comprises a VCO, first and second transistors, and first and second capacitive attenuators. The first and second transistors are cross coupled through the attenuators. In a first mode, the first and second transistors are turned off, and the capacitive attenuators attenuate a signal on output terminals of the VCO at control inputs of the first and second transistors. In another mode, the first and second transistors are turned on, and the capacitive attenuation is reduced or turned off so that control inputs of the first and second transistors receive signals on the outputs of the VCO.

A compound semiconductor device includes a compound semiconductor stacked structure, the compound semiconductor stacked structure including: an electron transit layer; an electron supply layer formed above the electron transit layer, the electron supply layer containing an n-type impurity; and a cap layer formed above the electron supply layer and containing the n-type impurity, in which in the electron supply layer, a concentration of the n-type impurity contained therein is non-uniform in a film thickness direction and a concentration of the n-type impurity in a surface of the cap layer side is lower than a maximum concentration of the n-type impurity in the electron supply layer.

A semiconductor apparatus includes a semiconductor chip including a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer. The gate electrode is formed in a comb shape having a plurality of tooth parts. An interval between the tooth parts becomes narrower from a center part toward a peripheral part of the semiconductor chip. The source electrode is formed on one of two sides of each of the tooth parts in the gate electrode, and the drain electrode is formed on another of the two sides. The source electrodes and the drain electrodes formed between the tooth parts in the gate electrode have respective areas that are substantially the same in a plan view.

A compound semiconductor device includes: a GaN-based channel layer; a barrier layer of nitride semiconductor above the channel layer; and a cap layer of nitride semiconductor above the barrier layer, wherein the cap layer includes: a first region doped with Fe; and a second region above the first region, a concentration of Fe in the second region being lower than a concentration of Fe in the first region.