A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting. To reduce distortion and more particularly, total harmonic distortion (THD), the amplifier output stage includes a substantially linear circuit configured to provide a bidirectional current sink for residual currents from the load occurring during at least part of each dead time interval.

An audio amplifier system is described comprising: a variable gain audio processor for processing digital audio signal, a digital to analog converter coupled to the audio processor, and configured to receive the processed digital audio signal, a variable gain amplifier having an input coupled to the output of the digital to analog converter and operably connected to a power supply, a controller coupled to the variable gain audio processor and the variable gain amplifier and configured to switch the audio amplifier system between a first operating mode having a first power supply voltage value and a second operating mode having a second higher power supply voltage value; wherein the controller is operable in the first operating mode to set the audio amplifier system gain to a desired gain value and in the second operating mode to maintain the desired gain value.

A sense amplifier circuit comprising a first-, second-, third- and fourth-amplification-blocks, each amplification-block comprising: an amplification-block-transistor comprising and an amplification-block-resistor. The amplification-block-transistor includes: a first-conduction-channel-terminal, a second-conduction-channel-terminal that is connected to an amplification-block-output-node, and a control-terminal that is connected to an amplification-block-control-node. The sense amplifier circuit also comprises: an amplification-block-resistor connected in series between an amplification-block-input-node and the first-conduction-channel-terminal; a first-bias-voltage-source connected to the amplification-block-control-nodes of the first- and third-amplification-blocks, a second-bias-voltage-source connected to the amplification-block-control-nodes of the second- and fourth-amplification-blocks. The sense amplifier circuit also comprises: a first-common-mode-voltage-resistor connected in series between a first-sensed-output-terminal and a common-mode-voltage-node; and a second-common-mode-voltage-resistor connected in series between a second-sensed-output-terminal and the common-mode-voltage-node.

An IC controller for USB Type-C device includes an error amplifier (EA), which includes an EA output coupled to a PWM comparator of a buck-boost converter; a first transconductance amplifier to adjust a current at the EA output, the first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier to adjust the current at the EA output, the second transconductance amplifier operating in a constant current mode. A first set of programmable registers is to store a first set of increasingly higher transconductance values. A second set of programmable registers is to store a second set of increasingly higher transconductance values. Control logic is to: cause the first transconductance amplifier to operate while sequentially using transconductance values stored in the first set of programmable registers; and cause the second transconductance amplifier to operate while sequentially using transconductance values stored in the second set of programmable registers.

An audio signal amplification device includes: a clock generation circuit that generates a clock for use in amplifying an audio signal; and a power supply circuit that generates direct current power, which is supplied to the clock generation circuit, from input power. The power supply circuit includes: a constant voltage generation circuit that generates direct current power of a constant voltage from the input power; a first capacitor; a first charging circuit that charges the first capacitor by using the input power; and a selection circuit. The selection circuit selects one direct current power of the direct current power generated in the constant voltage generation circuit and of direct current power charged to the first capacitor, and supplies the selected direct current power to the clock generation circuit.

A Bridge-Tied Load output self-oscillating class D amplifier includes a comparator receives an input signal from a signal input circuit at a second input terminal and outputs a positive-phase pulse width modulation signal and a reverse-phase pulse width modulation signal by comparing voltages of the two input terminal, first and second switching circuits power-amplifies the reverse-phase pulse width modulation signal and the positive-phase pulse width modulation signal, a first low-pass filter extracts a first output signal from the reverse-phase pulse width modulation signal, a second low-pass filter extracts a second output signal from the positive-phase pulse width modulation signal, a subtractor calculates a difference between the first and second output signals and output a difference signal, and a first feedback circuit feeds back the difference signal to the second input terminal of the comparator.

A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.

Certain aspects of the present disclosure provide an amplifier for signal amplification. Certain aspects further describe methods and apparatus for applying overload protection for such amplifier. For example, one method generally includes detecting an overload condition of an amplifier based on a signal at a node of the amplifier, and controlling a parameter of an input signal of the amplifier such that the parameter of the input signal is maintained below a threshold based on the detection of the overload condition. The parameter of the input signal may include, for example, a voltage level or a duty cycle of the input signal.

Certain aspects of the present disclosure provide methods and apparatus for dynamically managing the dead time between turning on output power stage transistors in amplifiers, such as audio amplifiers. One example method of operating an amplifier generally includes generating a drive signal based on an input signal; amplifying the drive signal by alternatively driving a first transistor and a second transistor with a time between deactivating the first transistor and activating the second transistor; and adjusting the time based on a parameter of the input signal or the drive signal, during the amplifying. For example, the parameter may include an amplitude of the input signal, a duty cycle of the drive signal, or a duty cycle of a modulated signal (e.g., a pulse-width modulated signal) generated based on the input signal. The input signal may be a digital audio input signal.

A class D amplifier includes a self-oscillating class D amplification circuit that is driven by an output current signal; and a voltage-current converting circuit that outputs an output current signal in response to an input signal voltage and an output signal voltage from a feedback signal voltage.