A digitally-controlled transimpedance amplifier (TIA) circuit is provided in which a plurality of feedback loops are digitally controlled, including, but not limited to, the DC offset cancellation loop, the variable gain control loop, and the TIA feedback impedance adjustment loop. The digitally-controlled TIA circuit includes digital loop-control circuitry that consumes less area on the TIA IC chip than the analog circuitry traditionally used to perform the feedback loop control in the analog domain. In addition, because digital logic continues to shrink as IC processes continue to evolve, the size of the IC chip packages will further decrease over time, leading to a smaller footprint in systems in which they are employed. The digital loop control circuitry is also capable of independently varying the gains of multiple gain stages of the variable gain control circuit to provide better control over the gain stages and better overall performance of the TIA circuit.

An amplifier arrangement comprises N amplifier stages (10.sub.1 to 10.sub.N). The amplifier arrangement comprises a main cascade of quarter wavelength transmission lines coupled between an output of a main amplifier (10.sub.2) of the N amplifier stages (10.sub.1 to 10.sub.N) and an output node (15) of the amplifier arrangement, wherein the main cascade comprises N−1 quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). An output of one peaking amplifier (10.sub.N) of the N amplifier stages is coupled to the output node (15), and remaining peaking amplifiers (10.sub.1, 10.sub.3 to 10.sub.N−1) of the N amplifier stages coupled to respective junctions (12.sub.1 to 12.sub.N−2) in the main cascade of quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). The amplifier arrangement is further configured such that at least one of the quarter wavelength transmission lines in the main cascade is extended by a half wavelength transmission line (13) or multiples of half wavelength transmission lines, and/or at least one of the peaking amplifiers (10−.sub.1, 10.sub.3 to 10.sub.N) is coupled to its respective junction or output node (15) via a connecting half wavelength transmission line (13) or multiples of half wavelength transmission lines.

A multistage linear power amplifier receiving an input signal. The multistage linear power amplifier comprises a plurality of Class-AB amplifiers connected in a cascade configuration. The plurality of Class-AB amplifiers amplifies the input signal to generate an amplified input signal. At least one of the plurality of Class-AB amplifiers is biased such that the multistage linear power amplifier emulates a Class-C amplifier.

An RF amplifier to increase a gain using a transformer is provided. The amplifier includes: a first transistor configured to generate a current by amplifying and converting an input voltage; a second transistor configured to amplify the generated current; and a first transformer configured to feed an emitter current of the second transistor back to a gate. Accordingly, G.sub.m of the transistor is boosted using the transformer, such that a high gain can be obtained with a low current. Therefore, a problem of a gain reduction caused by a parasitic capacitor at a high frequency can be solved.

A power amplifier circuit includes N (N is an integer equal to or greater than 2) power amplifier circuit cores, which in operation, amplify power of an input signal, N inductors, which in operation, are connected to the N power amplifier circuit cores, and ring-oscillator-type transconductance (gm) generation circuitry, which in operation, generates transconductance (gm) for compensating power loss of the N inductors.

A transformer includes multiple differential ports and first and second transformer windings. The first transformer winding includes a first transformer half-winding coupled to a first differential port of the differential ports. The first transformer winding also includes a second transformer half-winding coupled to a second differential port of the differential ports. An amplifier system that has a transformer is also provided. The amplifier system includes a first and a second stage amplifier. The first stage amplifier includes a first and a second amplifier. The second stage amplifier includes a third and a fourth amplifier. The transformer is coupled between the first stage amplifier and the second stage amplifier, where the transformer has a primary loop and a secondary loop. The primary loop of the transformer may be configured to receive differential signals of the first amplifier. A method for fabricating a transformer is also provided.

An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.

A power amplifier circuit includes an amplifier unit disposed on a die of a semiconductor device. The amplifier unit includes an amplifier transistor. The power amplifier circuit further includes a detector transistor disposed on the die of the semiconductor device, a variable attenuator that compensates for a gain of the amplifier unit, a bias level setting holding unit that holds a bias level setting value, which is set based on at least a detection value of the detector transistor, and a bias generation unit that generates a bias value of the variable attenuator based on the bias level setting value.

A solid state power amplifier uses a Doherty power amplifier that can be implemented as a monolithic microwave integrated circuit. By adjusting the DC bias of the amplifying stages in each branch of the Doherty amplifier, the output power, linearity, and DC power can be adjusted to provide a specified output, where the specification for the output can include the maintaining of desired DC power and linearity. The Doherty power amplifier can be used in a satellite payload or other application utilizing solid state power amplifiers, while providing the proper amount of RF output power and DC power. A single amplifier can have its bias levels adjusted for different output levels, helping to minimize the number of designs that are required for a given satellite payload, reducing the variety of parts in a satellite payload.