A method for calibrating a receiver of an isolator product includes adjusting a peaking frequency of a receiver signal path of a first integrated circuit die of the isolator product and a gain of the receiver signal path based on a predetermined peaking frequency, a predetermined gain, a first level of a diagnostic signal during a first interval, and a second level of the diagnostic signal during a second interval. The first interval and the second interval are non-overlapping intervals. The method may include receiving a calibration signal on a differential pair of nodes of the receiver signal path of the first integrated circuit die. The method may include generating a diagnostic signal corresponding to an average amplitude of a received version of the calibration signal.

A method for calibrating an isolator product includes receiving a calibration signal on a differential pair of nodes of a receiver signal path of a first integrated circuit die of the isolator product. The method includes generating a diagnostic signal having a level corresponding to an average amplitude of the calibration signal on the differential pair of nodes. The method includes configuring a programmable receiver signal path based on the diagnostic signal. Generating the diagnostic signal may include providing an analog signal based on a full-wave rectified version of the calibration signal on the differential pair of nodes. Generating the diagnostic signal may include converting the analog signal to a digital signal.

According to one embodiment, a semiconductor device includes an equalizer for receiving a first signal and outputting a second signal that has been adjusted to compensate for attenuation of the first signal. A filter is connected to the output terminal of the equalizer. A cancellation circuit operates to cancel a DC offset in the output of the equalizer. A processing circuit is configured to control the cancellation circuit to cancel the DC offset according to an output from the filter. The processing circuit sets a time constant for the filter to a first value to permit the cancellation circuit to cancel the DC offset when the equalizer is in a first state, and then sets the time constant to a second value when the equalizer is set to a second state to permit the cancellation circuit to cancel the DC offset when the equalizer is in the second state.

A first transmission line and a second transmission line that are connected in series to each other are disposed at different positions in a thickness direction of a substrate. A third transmission line is disposed between the first transmission line and the second transmission line in the thickness direction of the substrate. The third transmission line includes a first end portion connected to one end portion of the first transmission line, and a second end portion that is AC-grounded. The first transmission line and the second transmission line are electromagnetically coupled to the third transmission line.

A multistage amplifier includes: N amplifiers (N≥2), a (k+1).sup.th amplifier cascaded to a k.sup.th amplifier (1≤k≤N−1), and each amplifier being configured to amplify a multicarrier signal; and an extraction circuit including an input and an output, the input being connected to an output of a j.sup.th amplifier (1≤j≤N−1), and the output providing a compensation signal to an input of a (j+1).sup.th amplifier or an output of the (j+1).sup.th amplifier. The extraction circuit includes a filter circuit connected to the output of the j.sup.th amplifier that extracts a distortion frequency component of n times a differential frequency f2−f1 (n≥1), a phase shifter cascaded to the filter circuit that shifts a phase of the component, and a gain adjustment circuit cascaded to the phase shifter that adjusts an amplitude of the component and generates the compensation signal.

A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.

Embodiments of the disclosure generally relate to a multi-channel Doherty power amplifier, a multi-antenna transmitter, and a method for turning on the multi-channel Doherty amplifier. The multi-channel Doherty power amplifier includes: multiple input ports and the same number of output ports corresponding to multiple channels, the multiple channels having the same characteristics for radio signal amplification and transmission; multiple private peaking amplifiers corresponding to the multiple channels; and a common Doherty core shared by the multiple private peaking amplifiers. The multiple private peaking amplifiers and the common Doherty core are configured to amplify identical multi-channel signal for multiple inputs and multiple outputs, thus higher saving ratio and better channel performance (output power, linearity, efficiency, power gain etc.) consistency would be greatly improved.

A filter includes M filter circuits. The M filter circuits are sequentially cascaded from an input terminal to an output terminal, in order to generate an output signal according to an input signal, in which M is a positive integer greater than or equal to 2. The M filter circuits include at least one first filter circuit and at least one second filter circuit. Each of the at least one first filter circuit is set to be an active filter circuit, and each of the at least one second filter circuit is set to be a passive filter circuit.

A multi-radio access technology (RAT) envelope tracking (ET) amplifier apparatus is provided. The multi-RAT ET amplifier apparatus may be configured to enable concurrent communication of at least two radio frequency (RF) signals associated with at least two different RATs. Specifically, the multi-RAT ET amplifier apparatus includes an ET integrated circuit (IC) (ETIC) and a distributed ETIC (DETIC) configured to generate respective ET voltages for amplifying the two RF signals. In addition, the DETIC can be configured to utilize certain circuit(s) in the ETIC to help reduce a footprint of the DETIC. By amplifying the two different RF signals based on the respective ET voltages and sharing certain circuit(s) between the ETIC and the DETIC, it may be possible to improve overall efficiency and heat dissipation in the multi-RAT ET amplifier apparatus concurrent to reducing the footprint of the DETIC.

An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.